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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 362

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Rev	Log message	Author	Age	Path
362	added Makefiles to build project	unneback	4687d 00h	/ethmac/branches/unneback/rtl/verilog
361	created branch unneback	unneback	4687d 00h	/ethmac/branches/unneback/rtl/verilog
352	Removed delayed assignments from rtl code	olof	4698d 01h	/ethmac/branches/unneback/rtl/verilog
351	Turn defines into parameters in eth_cop	olof	4706d 15h	/ethmac/branches/unneback/rtl/verilog
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4706d 16h	/ethmac/branches/unneback/rtl/verilog
349	Make all parameters configurable from top level	olof	4707d 17h	/ethmac/branches/unneback/rtl/verilog
346	Updated project location	olof	4708d 18h	/ethmac/branches/unneback/rtl/verilog
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4718d 18h	/ethmac/branches/unneback/rtl/verilog
338		root	5512d 21h	/ethmac/branches/unneback/rtl/verilog
335	New directory structure.	root	5570d 02h	/ethmac/branches/unneback/rtl/verilog
333	Some small fixes + some troubles fixed.	igorm	7018d 16h	/ethmac/branches/unneback/rtl/verilog
332	Case statement improved for synthesys.	igorm	7031d 21h	/ethmac/branches/unneback/rtl/verilog
330	Warning fixes.	igorm	7046d 23h	/ethmac/branches/unneback/rtl/verilog
329	Defer indication fixed.	igorm	7047d 00h	/ethmac/branches/unneback/rtl/verilog
328	Delayed CRC fixed.	igorm	7047d 00h	/ethmac/branches/unneback/rtl/verilog
327	Defer indication fixed.	igorm	7047d 01h	/ethmac/branches/unneback/rtl/verilog
326	Delayed CRC fixed.	igorm	7047d 01h	/ethmac/branches/unneback/rtl/verilog
325	Defer indication fixed.	igorm	7047d 01h	/ethmac/branches/unneback/rtl/verilog
323	Accidently deleted line put back.	igorm	7344d 01h	/ethmac/branches/unneback/rtl/verilog
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7347d 20h	/ethmac/branches/unneback/rtl/verilog
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7348d 00h	/ethmac/branches/unneback/rtl/verilog
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7388d 02h	/ethmac/branches/unneback/rtl/verilog
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7490d 23h	/ethmac/branches/unneback/rtl/verilog
306	Lapsus fixed (!we -> ~we).	simons	7491d 21h	/ethmac/branches/unneback/rtl/verilog
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7513d 17h	/ethmac/branches/unneback/rtl/verilog
302	mbist signals updated according to newest convention	markom	7540d 04h	/ethmac/branches/unneback/rtl/verilog
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7550d 20h	/ethmac/branches/unneback/rtl/verilog
297	Artisan ram instance added.	simons	7603d 19h	/ethmac/branches/unneback/rtl/verilog
288	This file was not part of the RTL before, but it should be here.	simons	7639d 21h	/ethmac/branches/unneback/rtl/verilog
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7666d 00h	/ethmac/branches/unneback/rtl/verilog

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 362

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