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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 362

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Rev	Log message	Author	Age	Path
361	created branch unneback	unneback	4671d 20h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
352	Removed delayed assignments from rtl code	olof	4682d 22h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
349	Make all parameters configurable from top level	olof	4692d 13h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
346	Updated project location	olof	4693d 15h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
338		root	5497d 17h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
335	New directory structure.	root	5554d 22h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
333	Some small fixes + some troubles fixed.	igorm	7003d 12h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
327	Defer indication fixed.	igorm	7031d 21h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7332d 17h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7498d 14h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
302	mbist signals updated according to newest convention	markom	7525d 00h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7535d 16h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
276	Defer indication changed.	tadejm	7784d 19h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
272	When control packets were received, they were ignored in some cases.	tadejm	7792d 18h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7793d 20h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7854d 06h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
255	TPauseRq synchronized to tx_clk.	mohor	7855d 08h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
253	r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.	mohor	7856d 14h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7856d 15h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
248	wb_rst_i is used for MIIM reset.	mohor	7857d 15h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7861d 14h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7862d 10h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
227	Changed BIST scan signals.	tadejm	7888d 15h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
218	Typo error fixed. (When using Bist)	mohor	7895d 19h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
214	Signals for WISHBONE B3 compliant interface added.	mohor	7896d 15h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
210	BIST added.	mohor	7896d 16h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7916d 15h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7924d 17h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
164	Ethernet debug registers removed.	mohor	7926d 22h	/ethmac/branches/unneback/rtl/verilog/eth_top.v
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7927d 19h	/ethmac/branches/unneback/rtl/verilog/eth_top.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_top.v] - Rev 362

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