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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

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Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7983d 23h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7986d 02h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7989d 16h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7991d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7998d 14h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7999d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7999d 17h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7999d 20h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8067d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8076d 08h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8102d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8106d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8112d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8112d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8122d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8122d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8123d 10h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8128d 22h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8133d 00h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8133d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8144d 00h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8144d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8144d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8144d 20h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8147d 00h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8148d 08h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8151d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8153d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8154d 00h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8158d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

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