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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 352

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Rev	Log message	Author	Age	Path
352	Removed delayed assignments from rtl code	olof	4697d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
349	Make all parameters configurable from top level	olof	4706d 22h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
346	Updated project location	olof	4707d 23h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
338		root	5512d 02h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
335	New directory structure.	root	5569d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
333	Some small fixes + some troubles fixed.	igorm	7017d 21h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
329	Defer indication fixed.	igorm	7046d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
323	Accidently deleted line put back.	igorm	7343d 07h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7347d 02h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7512d 23h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
302	mbist signals updated according to newest convention	markom	7539d 09h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
280	Reset has priority in some flipflops.	mohor	7799d 02h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7799d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
272	When control packets were received, they were ignored in some cases.	tadejm	7807d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7808d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7809d 05h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7868d 04h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7868d 15h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7870d 23h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7876d 19h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7902d 20h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7903d 00h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7903d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7907d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7910d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
210	BIST added.	mohor	7911d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7940d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7941d 03h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
164	Ethernet debug registers removed.	mohor	7941d 06h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7943d 01h	/ethmac/branches/unneback/rtl/verilog/eth_wishbone.v

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 352

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