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[/] [ethmac/] [branches/] [unneback/] [rtl] - Rev 312

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Rev Log message Author Age Path
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7506d 13h /ethmac/branches/unneback/rtl
306 Lapsus fixed (!we -> ~we). simons 7507d 11h /ethmac/branches/unneback/rtl
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7529d 07h /ethmac/branches/unneback/rtl
302 mbist signals updated according to newest convention markom 7555d 18h /ethmac/branches/unneback/rtl
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7566d 10h /ethmac/branches/unneback/rtl
297 Artisan ram instance added. simons 7619d 09h /ethmac/branches/unneback/rtl
288 This file was not part of the RTL before, but it should be here. simons 7655d 11h /ethmac/branches/unneback/rtl
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7681d 14h /ethmac/branches/unneback/rtl
285 Binary operator used instead of unary (xnor). mohor 7681d 14h /ethmac/branches/unneback/rtl
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7709d 16h /ethmac/branches/unneback/rtl
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7737d 09h /ethmac/branches/unneback/rtl
280 Reset has priority in some flipflops. mohor 7815d 11h /ethmac/branches/unneback/rtl
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7815d 12h /ethmac/branches/unneback/rtl
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7815d 12h /ethmac/branches/unneback/rtl
276 Defer indication changed. tadejm 7815d 12h /ethmac/branches/unneback/rtl
275 Fix MTxErr or prevent sending too big frames. mohor 7822d 17h /ethmac/branches/unneback/rtl
272 When control packets were received, they were ignored in some cases. tadejm 7823d 12h /ethmac/branches/unneback/rtl
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7824d 14h /ethmac/branches/unneback/rtl
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7825d 14h /ethmac/branches/unneback/rtl
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7884d 12h /ethmac/branches/unneback/rtl
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7885d 00h /ethmac/branches/unneback/rtl
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7886d 01h /ethmac/branches/unneback/rtl
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7886d 02h /ethmac/branches/unneback/rtl
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7886d 02h /ethmac/branches/unneback/rtl
255 TPauseRq synchronized to tx_clk. mohor 7886d 02h /ethmac/branches/unneback/rtl
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7887d 08h /ethmac/branches/unneback/rtl
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7887d 08h /ethmac/branches/unneback/rtl
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7887d 08h /ethmac/branches/unneback/rtl
248 wb_rst_i is used for MIIM reset. mohor 7888d 08h /ethmac/branches/unneback/rtl
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7891d 11h /ethmac/branches/unneback/rtl

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