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[/] [ethmac/] [tags/] [asyst_3] - Rev 261

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Rev Log message Author Age Path
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7878d 00h /ethmac/tags/asyst_3
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7878d 12h /ethmac/tags/asyst_3
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7879d 01h /ethmac/tags/asyst_3
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7879d 02h /ethmac/tags/asyst_3
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7879d 02h /ethmac/tags/asyst_3
255 TPauseRq synchronized to tx_clk. mohor 7879d 02h /ethmac/tags/asyst_3
254 Temp version. mohor 7880d 05h /ethmac/tags/asyst_3
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7880d 08h /ethmac/tags/asyst_3
252 Just some updates. tadejm 7880d 08h /ethmac/tags/asyst_3
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7880d 08h /ethmac/tags/asyst_3
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7880d 08h /ethmac/tags/asyst_3
248 wb_rst_i is used for MIIM reset. mohor 7881d 08h /ethmac/tags/asyst_3
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7884d 11h /ethmac/tags/asyst_3
245 Rev 1.7. mohor 7885d 05h /ethmac/tags/asyst_3
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7885d 07h /ethmac/tags/asyst_3
243 Late collision is not reported any more. tadejm 7885d 13h /ethmac/tags/asyst_3
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7886d 03h /ethmac/tags/asyst_3
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7886d 03h /ethmac/tags/asyst_3
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7886d 03h /ethmac/tags/asyst_3
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7886d 03h /ethmac/tags/asyst_3
238 Defines fixed to use generic RAM by default. mohor 7898d 07h /ethmac/tags/asyst_3
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7900d 13h /ethmac/tags/asyst_3
235 rev 4. mohor 7901d 03h /ethmac/tags/asyst_3
234 Figure list assed to the revision 3. mohor 7901d 12h /ethmac/tags/asyst_3
233 Revision 0.3 released. Some figures added. mohor 7901d 12h /ethmac/tags/asyst_3
232 fpga define added. mohor 7906d 07h /ethmac/tags/asyst_3
231 Description of Core Modules added (figure). mohor 7908d 08h /ethmac/tags/asyst_3
229 case changed to casex. mohor 7912d 05h /ethmac/tags/asyst_3
227 Changed BIST scan signals. tadejm 7912d 09h /ethmac/tags/asyst_3
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7912d 10h /ethmac/tags/asyst_3

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