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Rev Log message Author Age Path
338 root 5515d 18h /ethmac/tags/rel_1
335 New directory structure. root 5573d 00h /ethmac/tags/rel_1
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7993d 17h /ethmac/tags/rel_1
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7993d 17h /ethmac/tags/rel_1
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7993d 17h /ethmac/tags/rel_1
120 Unused files removed. mohor 7993d 18h /ethmac/tags/rel_1
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7993d 18h /ethmac/tags/rel_1
118 ShiftEnded synchronization changed. mohor 7997d 09h /ethmac/tags/rel_1
117 Clock mrx_clk set to 2.5 MHz. mohor 7997d 20h /ethmac/tags/rel_1
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7997d 20h /ethmac/tags/rel_1
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7998d 17h /ethmac/tags/rel_1
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7999d 15h /ethmac/tags/rel_1
113 RxPointer bug fixed. mohor 8006d 07h /ethmac/tags/rel_1
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8006d 20h /ethmac/tags/rel_1
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8007d 10h /ethmac/tags/rel_1
110 m_wb_cyc_o signal released after every single transfer. mohor 8007d 13h /ethmac/tags/rel_1
109 Comment removed. mohor 8007d 13h /ethmac/tags/rel_1
108 Testbench supports unaligned accesses. mohor 8074d 23h /ethmac/tags/rel_1
107 TX_BUF_BASE changed. mohor 8074d 23h /ethmac/tags/rel_1
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8074d 23h /ethmac/tags/rel_1
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8084d 01h /ethmac/tags/rel_1
104 FCS should not be included in NibbleMinFl. mohor 8085d 19h /ethmac/tags/rel_1
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8085d 19h /ethmac/tags/rel_1
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8085d 20h /ethmac/tags/rel_1
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8085d 20h /ethmac/tags/rel_1
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8085d 20h /ethmac/tags/rel_1
99 Document revised. mohor 8092d 19h /ethmac/tags/rel_1
98 Document revised. mohor 8092d 19h /ethmac/tags/rel_1
97 Small typo fixed. lampret 8109d 17h /ethmac/tags/rel_1
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8113d 17h /ethmac/tags/rel_1

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