OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_1/] [rtl/] [verilog/] - Rev 113

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
113 RxPointer bug fixed. mohor 8017d 23h /ethmac/tags/rel_1/rtl/verilog
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8018d 12h /ethmac/tags/rel_1/rtl/verilog
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8019d 02h /ethmac/tags/rel_1/rtl/verilog
110 m_wb_cyc_o signal released after every single transfer. mohor 8019d 05h /ethmac/tags/rel_1/rtl/verilog
109 Comment removed. mohor 8019d 05h /ethmac/tags/rel_1/rtl/verilog
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8086d 15h /ethmac/tags/rel_1/rtl/verilog
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8095d 17h /ethmac/tags/rel_1/rtl/verilog
104 FCS should not be included in NibbleMinFl. mohor 8097d 11h /ethmac/tags/rel_1/rtl/verilog
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8097d 11h /ethmac/tags/rel_1/rtl/verilog
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8097d 12h /ethmac/tags/rel_1/rtl/verilog
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8097d 12h /ethmac/tags/rel_1/rtl/verilog
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8097d 12h /ethmac/tags/rel_1/rtl/verilog
97 Small typo fixed. lampret 8121d 09h /ethmac/tags/rel_1/rtl/verilog
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8125d 09h /ethmac/tags/rel_1/rtl/verilog
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8125d 12h /ethmac/tags/rel_1/rtl/verilog
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8125d 12h /ethmac/tags/rel_1/rtl/verilog
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8130d 10h /ethmac/tags/rel_1/rtl/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8131d 13h /ethmac/tags/rel_1/rtl/verilog
91 Comments in Slovene language removed. mohor 8131d 13h /ethmac/tags/rel_1/rtl/verilog
90 casex changed with case, fifo reset changed. mohor 8131d 13h /ethmac/tags/rel_1/rtl/verilog
88 rx_fifo was not always cleared ok. Fixed. mohor 8141d 10h /ethmac/tags/rel_1/rtl/verilog
87 Status was not latched correctly sometimes. Fixed. mohor 8141d 12h /ethmac/tags/rel_1/rtl/verilog
86 Big Endian problem when sending frames fixed. mohor 8142d 19h /ethmac/tags/rel_1/rtl/verilog
85 Log info was missing. mohor 8148d 05h /ethmac/tags/rel_1/rtl/verilog
84 LinkFail signal was not latching appropriate bit. mohor 8148d 05h /ethmac/tags/rel_1/rtl/verilog
83 MAC address recognition was not correct (bytes swaped). mohor 8148d 05h /ethmac/tags/rel_1/rtl/verilog
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8148d 06h /ethmac/tags/rel_1/rtl/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8152d 09h /ethmac/tags/rel_1/rtl/verilog
79 RetryCntLatched was unused and removed from design mohor 8152d 09h /ethmac/tags/rel_1/rtl/verilog
78 WB_SEL_I was unused and removed from design mohor 8152d 09h /ethmac/tags/rel_1/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.