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[/] [ethmac/] [tags/] [rel_1/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 123

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123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7987d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7987d 19h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7991d 10h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7992d 19h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 8000d 08h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8000d 22h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8001d 11h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 8001d 14h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8069d 00h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8078d 02h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8103d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8107d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8113d 22h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8113d 22h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8123d 19h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8123d 21h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8125d 04h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8130d 16h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8134d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8134d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8145d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8145d 22h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8145d 23h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8146d 14h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8148d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
43 Tx status is written back to the BD. mohor 8150d 01h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
42 Rx status is written back to the BD. mohor 8152d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8154d 21h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8155d 18h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8159d 22h /ethmac/tags/rel_1/rtl/verilog/eth_wishbone.v

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