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45 Ethernet Datasheet added. mohor 8172d 09h /ethmac/tags/rel_1
44 Ethernet Datasheet added to cvs. mohor 8172d 09h /ethmac/tags/rel_1
43 Tx status is written back to the BD. mohor 8173d 11h /ethmac/tags/rel_1
42 Rx status is written back to the BD. mohor 8176d 04h /ethmac/tags/rel_1
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8178d 06h /ethmac/tags/rel_1
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8179d 03h /ethmac/tags/rel_1
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8183d 07h /ethmac/tags/rel_1
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8192d 09h /ethmac/tags/rel_1
37 Link in the header changed. mohor 8192d 09h /ethmac/tags/rel_1
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8238d 07h /ethmac/tags/rel_1
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8241d 05h /ethmac/tags/rel_1
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8241d 05h /ethmac/tags/rel_1
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8241d 09h /ethmac/tags/rel_1
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8241d 10h /ethmac/tags/rel_1
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8241d 10h /ethmac/tags/rel_1
30 BD section updated. mohor 8243d 07h /ethmac/tags/rel_1
29 Generic memory model is used. Defines are changed for the same reason. mohor 8263d 06h /ethmac/tags/rel_1
28 New release. Name changed to lower case. mohor 8265d 21h /ethmac/tags/rel_1
27 File names changed to lower case. mohor 8265d 21h /ethmac/tags/rel_1
26 First release of product brief. mohor 8265d 21h /ethmac/tags/rel_1
25 First release of product brief. mohor 8265d 21h /ethmac/tags/rel_1
24 Log file added. mohor 8288d 08h /ethmac/tags/rel_1
23 Number of addresses (wb_adr_i) minimized. mohor 8288d 09h /ethmac/tags/rel_1
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8288d 11h /ethmac/tags/rel_1
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8289d 08h /ethmac/tags/rel_1
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8313d 05h /ethmac/tags/rel_1
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8313d 05h /ethmac/tags/rel_1
18 Few little NCSIM warnings fixed. mohor 8326d 06h /ethmac/tags/rel_1
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8353d 06h /ethmac/tags/rel_1
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8360d 11h /ethmac/tags/rel_1

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