OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_10] - Rev 179

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
179 Beautiful tests merget together mohor 7954d 00h /ethmac/tags/rel_10
178 Rearanged testcases mohor 7954d 00h /ethmac/tags/rel_10
177 Bug in MIIM fixed. mohor 7954d 03h /ethmac/tags/rel_10
176 lists changed to new directory structure mohor 7954d 05h /ethmac/tags/rel_10
175 Script fixed to new dir structure mohor 7954d 05h /ethmac/tags/rel_10
174 Directory keeper mohor 7954d 05h /ethmac/tags/rel_10
173 Keeps the directory mohor 7954d 05h /ethmac/tags/rel_10
172 NCSIM simulation environment added to cvs mohor 7954d 05h /ethmac/tags/rel_10
171 NCSIM simulation environment added. mohor 7954d 05h /ethmac/tags/rel_10
170 Headers changed. mohor 7954d 06h /ethmac/tags/rel_10
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7954d 06h /ethmac/tags/rel_10
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7955d 03h /ethmac/tags/rel_10
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7956d 04h /ethmac/tags/rel_10
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7957d 04h /ethmac/tags/rel_10
165 HASH improvement needed. mohor 7957d 08h /ethmac/tags/rel_10
164 Ethernet debug registers removed. mohor 7957d 08h /ethmac/tags/rel_10
163 Another temporary version. Core is almost finished. Testbench not included,
yet"
mohor 7958d 00h /ethmac/tags/rel_10
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 7958d 00h /ethmac/tags/rel_10
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7958d 05h /ethmac/tags/rel_10
160 error acknowledge cycle termination added to display. mohor 7958d 05h /ethmac/tags/rel_10
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7959d 02h /ethmac/tags/rel_10
158 Typo fixed. mohor 7959d 02h /ethmac/tags/rel_10
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7961d 07h /ethmac/tags/rel_10
156 Valid testbench. mohor 7961d 07h /ethmac/tags/rel_10
155 Minor changes. mohor 7961d 07h /ethmac/tags/rel_10
154 Design document is still under construction. mohor 7962d 06h /ethmac/tags/rel_10
153 Temp version (backup). mohor 7962d 22h /ethmac/tags/rel_10
152 Version 1.16 created. See revision history in the document for details. mohor 7962d 22h /ethmac/tags/rel_10
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7962d 23h /ethmac/tags/rel_10
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 7963d 00h /ethmac/tags/rel_10

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.