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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7890d 01h /ethmac/tags/rel_12
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7892d 07h /ethmac/tags/rel_12
235 rev 4. mohor 7892d 21h /ethmac/tags/rel_12
234 Figure list assed to the revision 3. mohor 7893d 05h /ethmac/tags/rel_12
233 Revision 0.3 released. Some figures added. mohor 7893d 06h /ethmac/tags/rel_12
232 fpga define added. mohor 7898d 01h /ethmac/tags/rel_12
231 Description of Core Modules added (figure). mohor 7900d 02h /ethmac/tags/rel_12
229 case changed to casex. mohor 7903d 23h /ethmac/tags/rel_12
227 Changed BIST scan signals. tadejm 7904d 02h /ethmac/tags/rel_12
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7904d 04h /ethmac/tags/rel_12
225 Some minor changes. tadejm 7904d 04h /ethmac/tags/rel_12
224 Signals for a wave window in Modelsim. tadejm 7904d 05h /ethmac/tags/rel_12
223 Some code changed due to bug fixes. tadejm 7904d 05h /ethmac/tags/rel_12
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7908d 03h /ethmac/tags/rel_12
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7911d 04h /ethmac/tags/rel_12
218 Typo error fixed. (When using Bist) mohor 7911d 06h /ethmac/tags/rel_12
217 Bist supported. mohor 7911d 06h /ethmac/tags/rel_12
216 Bist signals added. mohor 7911d 06h /ethmac/tags/rel_12
215 Bist supported. mohor 7911d 07h /ethmac/tags/rel_12
214 Signals for WISHBONE B3 compliant interface added. mohor 7912d 03h /ethmac/tags/rel_12
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7912d 03h /ethmac/tags/rel_12
212 Minor $display change. mohor 7912d 03h /ethmac/tags/rel_12
211 Bist added. mohor 7912d 03h /ethmac/tags/rel_12
210 BIST added. mohor 7912d 03h /ethmac/tags/rel_12
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7913d 06h /ethmac/tags/rel_12
208 Virtual Silicon RAMs moved to lib directory tadej 7929d 00h /ethmac/tags/rel_12
207 Virtual Silicon RAM support fixed tadej 7929d 00h /ethmac/tags/rel_12
206 Virtual Silicon RAM added to the simulation. mohor 7929d 00h /ethmac/tags/rel_12
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7929d 01h /ethmac/tags/rel_12
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7929d 01h /ethmac/tags/rel_12

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