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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] - Rev 127

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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7989d 00h /ethmac/tags/rel_14/rtl/verilog
126 InvalidSymbol generation changed. mohor 7989d 01h /ethmac/tags/rel_14/rtl/verilog
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7989d 01h /ethmac/tags/rel_14/rtl/verilog
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7991d 02h /ethmac/tags/rel_14/rtl/verilog
120 Unused files removed. mohor 7991d 03h /ethmac/tags/rel_14/rtl/verilog
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7991d 03h /ethmac/tags/rel_14/rtl/verilog
118 ShiftEnded synchronization changed. mohor 7994d 18h /ethmac/tags/rel_14/rtl/verilog
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7996d 03h /ethmac/tags/rel_14/rtl/verilog
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7997d 00h /ethmac/tags/rel_14/rtl/verilog
113 RxPointer bug fixed. mohor 8003d 16h /ethmac/tags/rel_14/rtl/verilog
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8004d 06h /ethmac/tags/rel_14/rtl/verilog
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8004d 19h /ethmac/tags/rel_14/rtl/verilog
110 m_wb_cyc_o signal released after every single transfer. mohor 8004d 22h /ethmac/tags/rel_14/rtl/verilog
109 Comment removed. mohor 8004d 23h /ethmac/tags/rel_14/rtl/verilog
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8072d 09h /ethmac/tags/rel_14/rtl/verilog
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8081d 10h /ethmac/tags/rel_14/rtl/verilog
104 FCS should not be included in NibbleMinFl. mohor 8083d 04h /ethmac/tags/rel_14/rtl/verilog
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8083d 05h /ethmac/tags/rel_14/rtl/verilog
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8083d 05h /ethmac/tags/rel_14/rtl/verilog
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8083d 05h /ethmac/tags/rel_14/rtl/verilog
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8083d 05h /ethmac/tags/rel_14/rtl/verilog
97 Small typo fixed. lampret 8107d 03h /ethmac/tags/rel_14/rtl/verilog
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8111d 03h /ethmac/tags/rel_14/rtl/verilog
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8111d 05h /ethmac/tags/rel_14/rtl/verilog
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8111d 05h /ethmac/tags/rel_14/rtl/verilog
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8116d 04h /ethmac/tags/rel_14/rtl/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8117d 06h /ethmac/tags/rel_14/rtl/verilog
91 Comments in Slovene language removed. mohor 8117d 06h /ethmac/tags/rel_14/rtl/verilog
90 casex changed with case, fifo reset changed. mohor 8117d 06h /ethmac/tags/rel_14/rtl/verilog
88 rx_fifo was not always cleared ok. Fixed. mohor 8127d 03h /ethmac/tags/rel_14/rtl/verilog

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