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[/] [ethmac/] [tags/] [rel_14] - Rev 241

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241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7895d 00h /ethmac/tags/rel_14
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7895d 00h /ethmac/tags/rel_14
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7895d 01h /ethmac/tags/rel_14
238 Defines fixed to use generic RAM by default. mohor 7907d 05h /ethmac/tags/rel_14
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7909d 10h /ethmac/tags/rel_14
235 rev 4. mohor 7910d 01h /ethmac/tags/rel_14
234 Figure list assed to the revision 3. mohor 7910d 09h /ethmac/tags/rel_14
233 Revision 0.3 released. Some figures added. mohor 7910d 09h /ethmac/tags/rel_14
232 fpga define added. mohor 7915d 04h /ethmac/tags/rel_14
231 Description of Core Modules added (figure). mohor 7917d 05h /ethmac/tags/rel_14
229 case changed to casex. mohor 7921d 02h /ethmac/tags/rel_14
227 Changed BIST scan signals. tadejm 7921d 06h /ethmac/tags/rel_14
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7921d 07h /ethmac/tags/rel_14
225 Some minor changes. tadejm 7921d 07h /ethmac/tags/rel_14
224 Signals for a wave window in Modelsim. tadejm 7921d 09h /ethmac/tags/rel_14
223 Some code changed due to bug fixes. tadejm 7921d 09h /ethmac/tags/rel_14
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7925d 07h /ethmac/tags/rel_14
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7928d 07h /ethmac/tags/rel_14
218 Typo error fixed. (When using Bist) mohor 7928d 09h /ethmac/tags/rel_14
217 Bist supported. mohor 7928d 09h /ethmac/tags/rel_14
216 Bist signals added. mohor 7928d 09h /ethmac/tags/rel_14
215 Bist supported. mohor 7928d 10h /ethmac/tags/rel_14
214 Signals for WISHBONE B3 compliant interface added. mohor 7929d 06h /ethmac/tags/rel_14
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7929d 06h /ethmac/tags/rel_14
212 Minor $display change. mohor 7929d 06h /ethmac/tags/rel_14
211 Bist added. mohor 7929d 06h /ethmac/tags/rel_14
210 BIST added. mohor 7929d 06h /ethmac/tags/rel_14
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7930d 10h /ethmac/tags/rel_14
208 Virtual Silicon RAMs moved to lib directory tadej 7946d 03h /ethmac/tags/rel_14
207 Virtual Silicon RAM support fixed tadej 7946d 04h /ethmac/tags/rel_14

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