OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 338

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
338 root 5545d 12h /ethmac/tags/rel_15/rtl/verilog
335 New directory structure. root 5602d 17h /ethmac/tags/rel_15/rtl/verilog
273 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7840d 13h /ethmac/tags/rel_15/rtl/verilog
272 When control packets were received, they were ignored in some cases. tadejm 7840d 13h /ethmac/tags/rel_15/rtl/verilog
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7841d 15h /ethmac/tags/rel_15/rtl/verilog
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7842d 15h /ethmac/tags/rel_15/rtl/verilog
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7901d 14h /ethmac/tags/rel_15/rtl/verilog
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7902d 01h /ethmac/tags/rel_15/rtl/verilog
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7903d 02h /ethmac/tags/rel_15/rtl/verilog
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7903d 03h /ethmac/tags/rel_15/rtl/verilog
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7903d 03h /ethmac/tags/rel_15/rtl/verilog
255 TPauseRq synchronized to tx_clk. mohor 7903d 03h /ethmac/tags/rel_15/rtl/verilog
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7904d 09h /ethmac/tags/rel_15/rtl/verilog
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7904d 09h /ethmac/tags/rel_15/rtl/verilog
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7904d 09h /ethmac/tags/rel_15/rtl/verilog
248 wb_rst_i is used for MIIM reset. mohor 7905d 10h /ethmac/tags/rel_15/rtl/verilog
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7908d 13h /ethmac/tags/rel_15/rtl/verilog
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7909d 08h /ethmac/tags/rel_15/rtl/verilog
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7910d 05h /ethmac/tags/rel_15/rtl/verilog
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7910d 05h /ethmac/tags/rel_15/rtl/verilog
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7910d 05h /ethmac/tags/rel_15/rtl/verilog
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7910d 05h /ethmac/tags/rel_15/rtl/verilog
238 Defines fixed to use generic RAM by default. mohor 7922d 09h /ethmac/tags/rel_15/rtl/verilog
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7924d 14h /ethmac/tags/rel_15/rtl/verilog
232 fpga define added. mohor 7930d 08h /ethmac/tags/rel_15/rtl/verilog
229 case changed to casex. mohor 7936d 06h /ethmac/tags/rel_15/rtl/verilog
227 Changed BIST scan signals. tadejm 7936d 10h /ethmac/tags/rel_15/rtl/verilog
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7936d 11h /ethmac/tags/rel_15/rtl/verilog
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7940d 11h /ethmac/tags/rel_15/rtl/verilog
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7943d 11h /ethmac/tags/rel_15/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.