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[/] [ethmac/] [tags/] [rel_15] - Rev 130

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130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.		 mohor 7992d 04h /ethmac/tags/rel_15
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface		 mohor 7992d 04h /ethmac/tags/rel_15
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 8012d 03h /ethmac/tags/rel_15
126 InvalidSymbol generation changed. mohor 8012d 03h /ethmac/tags/rel_15
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 8012d 03h /ethmac/tags/rel_15
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8012d 04h /ethmac/tags/rel_15
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8014d 05h /ethmac/tags/rel_15
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8014d 05h /ethmac/tags/rel_15
120 Unused files removed. mohor 8014d 06h /ethmac/tags/rel_15
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8014d 06h /ethmac/tags/rel_15
118 ShiftEnded synchronization changed. mohor 8017d 21h /ethmac/tags/rel_15
117 Clock mrx_clk set to 2.5 MHz. mohor 8018d 07h /ethmac/tags/rel_15
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8018d 08h /ethmac/tags/rel_15
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8019d 05h /ethmac/tags/rel_15
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8020d 03h /ethmac/tags/rel_15
113 RxPointer bug fixed. mohor 8026d 19h /ethmac/tags/rel_15
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8027d 08h /ethmac/tags/rel_15
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8027d 22h /ethmac/tags/rel_15
110 m_wb_cyc_o signal released after every single transfer. mohor 8028d 01h /ethmac/tags/rel_15
109 Comment removed. mohor 8028d 01h /ethmac/tags/rel_15
108 Testbench supports unaligned accesses. mohor 8095d 11h /ethmac/tags/rel_15
107 TX_BUF_BASE changed. mohor 8095d 11h /ethmac/tags/rel_15
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8095d 11h /ethmac/tags/rel_15
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8104d 13h /ethmac/tags/rel_15
104 FCS should not be included in NibbleMinFl. mohor 8106d 07h /ethmac/tags/rel_15
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8106d 07h /ethmac/tags/rel_15
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8106d 07h /ethmac/tags/rel_15
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8106d 08h /ethmac/tags/rel_15
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8106d 08h /ethmac/tags/rel_15
99 Document revised. mohor 8113d 06h /ethmac/tags/rel_15

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