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[/] [ethmac/] [tags/] [rel_16/] [bench/] [verilog/] - Rev 365

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Rev	Log message	Author	Age	Path
338		root	5525d 13h	/ethmac/tags/rel_16/bench/verilog
335	New directory structure.	root	5582d 19h	/ethmac/tags/rel_16/bench/verilog
282	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7811d 13h	/ethmac/tags/rel_16/bench/verilog
281	Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.	mohor	7811d 13h	/ethmac/tags/rel_16/bench/verilog
279	Underrun test fixed. Many other tests fixed.	mohor	7812d 15h	/ethmac/tags/rel_16/bench/verilog
274	Backup version. Not fully working.	tadejm	7820d 09h	/ethmac/tags/rel_16/bench/verilog
267	Full duplex control frames tested.	mohor	7876d 12h	/ethmac/tags/rel_16/bench/verilog
266	Flow control test almost finished.	mohor	7881d 11h	/ethmac/tags/rel_16/bench/verilog
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7882d 03h	/ethmac/tags/rel_16/bench/verilog
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7882d 15h	/ethmac/tags/rel_16/bench/verilog
254	Temp version.	mohor	7884d 08h	/ethmac/tags/rel_16/bench/verilog
252	Just some updates.	tadejm	7884d 11h	/ethmac/tags/rel_16/bench/verilog
243	Late collision is not reported any more.	tadejm	7889d 16h	/ethmac/tags/rel_16/bench/verilog
227	Changed BIST scan signals.	tadejm	7916d 12h	/ethmac/tags/rel_16/bench/verilog
223	Some code changed due to bug fixes.	tadejm	7916d 15h	/ethmac/tags/rel_16/bench/verilog
216	Bist signals added.	mohor	7923d 15h	/ethmac/tags/rel_16/bench/verilog
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7925d 16h	/ethmac/tags/rel_16/bench/verilog
194	Full duplex tests modified and testbench bug repaired.	tadej	7944d 14h	/ethmac/tags/rel_16/bench/verilog
192	Some additional reports added	tadej	7946d 11h	/ethmac/tags/rel_16/bench/verilog
191	Bug repaired in eth_phy device	tadej	7946d 11h	/ethmac/tags/rel_16/bench/verilog
189	Simple testbench that includes eth_cop, eth_host and eth_memory modules. This testbench is used for testing the whole environment. Use tb_ethernet testbench for testing just the ethernet MAC core (many tests).	mohor	7946d 12h	/ethmac/tags/rel_16/bench/verilog
188	PHY changed.	tadej	7947d 09h	/ethmac/tags/rel_16/bench/verilog
182	Full duplex test improved.	tadej	7948d 11h	/ethmac/tags/rel_16/bench/verilog
181	MIIM test look better.	mohor	7948d 14h	/ethmac/tags/rel_16/bench/verilog
180	Bench outputs data to display every 128 bytes.	mohor	7951d 09h	/ethmac/tags/rel_16/bench/verilog
179	Beautiful tests merget together	mohor	7951d 10h	/ethmac/tags/rel_16/bench/verilog
178	Rearanged testcases	mohor	7951d 10h	/ethmac/tags/rel_16/bench/verilog
177	Bug in MIIM fixed.	mohor	7951d 14h	/ethmac/tags/rel_16/bench/verilog
170	Headers changed.	mohor	7951d 16h	/ethmac/tags/rel_16/bench/verilog
169	New testbench. Thanks to Tadej M - "The Spammer".	mohor	7951d 17h	/ethmac/tags/rel_16/bench/verilog

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[/] [ethmac/] [tags/] [rel_16/] [bench/] [verilog/] - Rev 365

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