OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_16] - Rev 256

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7873d 15h /ethmac/tags/rel_16
255 TPauseRq synchronized to tx_clk. mohor 7873d 15h /ethmac/tags/rel_16
254 Temp version. mohor 7874d 19h /ethmac/tags/rel_16
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7874d 21h /ethmac/tags/rel_16
252 Just some updates. tadejm 7874d 21h /ethmac/tags/rel_16
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7874d 21h /ethmac/tags/rel_16
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7874d 21h /ethmac/tags/rel_16
248 wb_rst_i is used for MIIM reset. mohor 7875d 22h /ethmac/tags/rel_16
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7879d 01h /ethmac/tags/rel_16
245 Rev 1.7. mohor 7879d 18h /ethmac/tags/rel_16
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7879d 20h /ethmac/tags/rel_16
243 Late collision is not reported any more. tadejm 7880d 02h /ethmac/tags/rel_16
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7880d 17h /ethmac/tags/rel_16
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7880d 17h /ethmac/tags/rel_16
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7880d 17h /ethmac/tags/rel_16
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7880d 17h /ethmac/tags/rel_16
238 Defines fixed to use generic RAM by default. mohor 7892d 21h /ethmac/tags/rel_16
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7895d 02h /ethmac/tags/rel_16
235 rev 4. mohor 7895d 17h /ethmac/tags/rel_16
234 Figure list assed to the revision 3. mohor 7896d 01h /ethmac/tags/rel_16
233 Revision 0.3 released. Some figures added. mohor 7896d 01h /ethmac/tags/rel_16
232 fpga define added. mohor 7900d 20h /ethmac/tags/rel_16
231 Description of Core Modules added (figure). mohor 7902d 21h /ethmac/tags/rel_16
229 case changed to casex. mohor 7906d 18h /ethmac/tags/rel_16
227 Changed BIST scan signals. tadejm 7906d 22h /ethmac/tags/rel_16
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7906d 23h /ethmac/tags/rel_16
225 Some minor changes. tadejm 7907d 00h /ethmac/tags/rel_16
224 Signals for a wave window in Modelsim. tadejm 7907d 01h /ethmac/tags/rel_16
223 Some code changed due to bug fixes. tadejm 7907d 01h /ethmac/tags/rel_16
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7910d 23h /ethmac/tags/rel_16

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.