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Rev Log message Author Age Path
187 _info file added. mohor 7964d 00h /ethmac/tags/rel_17
186 Macro for testbench (DO file). mohor 7964d 00h /ethmac/tags/rel_17
185 Directory keeper. mohor 7964d 00h /ethmac/tags/rel_17
184 Modelsim simulation environment should be ready now. mohor 7964d 01h /ethmac/tags/rel_17
183 Modelsim environment added. mohor 7964d 01h /ethmac/tags/rel_17
182 Full duplex test improved. tadej 7965d 02h /ethmac/tags/rel_17
181 MIIM test look better. mohor 7965d 04h /ethmac/tags/rel_17
180 Bench outputs data to display every 128 bytes. mohor 7968d 00h /ethmac/tags/rel_17
179 Beautiful tests merget together mohor 7968d 01h /ethmac/tags/rel_17
178 Rearanged testcases mohor 7968d 01h /ethmac/tags/rel_17
177 Bug in MIIM fixed. mohor 7968d 05h /ethmac/tags/rel_17
176 lists changed to new directory structure mohor 7968d 06h /ethmac/tags/rel_17
175 Script fixed to new dir structure mohor 7968d 06h /ethmac/tags/rel_17
174 Directory keeper mohor 7968d 06h /ethmac/tags/rel_17
173 Keeps the directory mohor 7968d 06h /ethmac/tags/rel_17
172 NCSIM simulation environment added to cvs mohor 7968d 06h /ethmac/tags/rel_17
171 NCSIM simulation environment added. mohor 7968d 07h /ethmac/tags/rel_17
170 Headers changed. mohor 7968d 07h /ethmac/tags/rel_17
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7968d 07h /ethmac/tags/rel_17
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7969d 05h /ethmac/tags/rel_17
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7970d 05h /ethmac/tags/rel_17
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7971d 06h /ethmac/tags/rel_17
165 HASH improvement needed. mohor 7971d 09h /ethmac/tags/rel_17
164 Ethernet debug registers removed. mohor 7971d 09h /ethmac/tags/rel_17
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7972d 01h /ethmac/tags/rel_17
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7972d 01h /ethmac/tags/rel_17
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7972d 06h /ethmac/tags/rel_17
160 error acknowledge cycle termination added to display. mohor 7972d 07h /ethmac/tags/rel_17
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7973d 03h /ethmac/tags/rel_17
158 Typo fixed. mohor 7973d 03h /ethmac/tags/rel_17

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