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[/] [ethmac/] [tags/] [rel_17/] - Rev 46

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46 HASH0 and HASH1 registers added. mohor 8243d 13h /ethmac/tags/rel_17
45 Ethernet Datasheet added. mohor 8243d 19h /ethmac/tags/rel_17
44 Ethernet Datasheet added to cvs. mohor 8243d 19h /ethmac/tags/rel_17
43 Tx status is written back to the BD. mohor 8244d 21h /ethmac/tags/rel_17
42 Rx status is written back to the BD. mohor 8247d 14h /ethmac/tags/rel_17
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8249d 16h /ethmac/tags/rel_17
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8250d 13h /ethmac/tags/rel_17
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8254d 17h /ethmac/tags/rel_17
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8263d 19h /ethmac/tags/rel_17
37 Link in the header changed. mohor 8263d 19h /ethmac/tags/rel_17
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8309d 17h /ethmac/tags/rel_17
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8312d 15h /ethmac/tags/rel_17
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8312d 15h /ethmac/tags/rel_17
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8312d 19h /ethmac/tags/rel_17
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8312d 20h /ethmac/tags/rel_17
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8312d 20h /ethmac/tags/rel_17
30 BD section updated. mohor 8314d 17h /ethmac/tags/rel_17
29 Generic memory model is used. Defines are changed for the same reason. mohor 8334d 15h /ethmac/tags/rel_17
28 New release. Name changed to lower case. mohor 8337d 07h /ethmac/tags/rel_17
27 File names changed to lower case. mohor 8337d 07h /ethmac/tags/rel_17
26 First release of product brief. mohor 8337d 07h /ethmac/tags/rel_17
25 First release of product brief. mohor 8337d 07h /ethmac/tags/rel_17
24 Log file added. mohor 8359d 18h /ethmac/tags/rel_17
23 Number of addresses (wb_adr_i) minimized. mohor 8359d 18h /ethmac/tags/rel_17
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8359d 21h /ethmac/tags/rel_17
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8360d 18h /ethmac/tags/rel_17
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8384d 15h /ethmac/tags/rel_17
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8384d 15h /ethmac/tags/rel_17
18 Few little NCSIM warnings fixed. mohor 8397d 16h /ethmac/tags/rel_17
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8424d 16h /ethmac/tags/rel_17

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