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[/] [ethmac/] [tags/] [rel_17/] [bench/] [verilog/] [tb_ethernet.v] - Rev 347

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338 root 5532d 03h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
335 New directory structure. root 5589d 08h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
287 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7685d 06h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7818d 02h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7819d 05h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7826d 23h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7883d 02h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7888d 01h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7888d 16h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7889d 04h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7890d 22h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7891d 01h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7896d 05h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7923d 01h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7923d 04h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7932d 05h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7951d 04h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7953d 00h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7955d 00h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7955d 03h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7957d 23h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7958d 00h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7958d 00h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7958d 03h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7958d 06h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7958d 06h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 7963d 02h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 7965d 07h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8010d 02h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v
117 Clock mrx_clk set to 2.5 MHz. mohor 8014d 04h /ethmac/tags/rel_17/bench/verilog/tb_ethernet.v

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