OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 166

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7939d 01h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7939d 04h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7940d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7944d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7965d 19h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7985d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7987d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7991d 14h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7992d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 8000d 12h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8001d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8001d 15h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 8001d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8069d 05h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8078d 06h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8103d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8107d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8114d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8114d 02h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8123d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8124d 01h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8125d 08h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8130d 20h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8134d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8134d 23h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8145d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8146d 03h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8146d 18h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8148d 22h /ethmac/tags/rel_17/rtl/verilog/eth_wishbone.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.