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[/] [ethmac/] [tags/] [rel_17] - Rev 110

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Rev Log message Author Age Path
110 m_wb_cyc_o signal released after every single transfer. mohor 8038d 07h /ethmac/tags/rel_17
109 Comment removed. mohor 8038d 08h /ethmac/tags/rel_17
108 Testbench supports unaligned accesses. mohor 8105d 17h /ethmac/tags/rel_17
107 TX_BUF_BASE changed. mohor 8105d 17h /ethmac/tags/rel_17
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8105d 18h /ethmac/tags/rel_17
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8114d 19h /ethmac/tags/rel_17
104 FCS should not be included in NibbleMinFl. mohor 8116d 13h /ethmac/tags/rel_17
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8116d 14h /ethmac/tags/rel_17
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8116d 14h /ethmac/tags/rel_17
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8116d 14h /ethmac/tags/rel_17
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8116d 14h /ethmac/tags/rel_17
99 Document revised. mohor 8123d 13h /ethmac/tags/rel_17
98 Document revised. mohor 8123d 13h /ethmac/tags/rel_17
97 Small typo fixed. lampret 8140d 12h /ethmac/tags/rel_17
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8144d 12h /ethmac/tags/rel_17
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8144d 14h /ethmac/tags/rel_17
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 8144d 14h /ethmac/tags/rel_17
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 8149d 13h /ethmac/tags/rel_17
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8150d 15h /ethmac/tags/rel_17
91 Comments in Slovene language removed. mohor 8150d 15h /ethmac/tags/rel_17
90 casex changed with case, fifo reset changed. mohor 8150d 15h /ethmac/tags/rel_17
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.		 mohor 8154d 13h /ethmac/tags/rel_17
88 rx_fifo was not always cleared ok. Fixed. mohor 8160d 12h /ethmac/tags/rel_17
87 Status was not latched correctly sometimes. Fixed. mohor 8160d 14h /ethmac/tags/rel_17
86 Big Endian problem when sending frames fixed. mohor 8161d 21h /ethmac/tags/rel_17
85 Log info was missing. mohor 8167d 07h /ethmac/tags/rel_17
84 LinkFail signal was not latching appropriate bit. mohor 8167d 07h /ethmac/tags/rel_17
83 MAC address recognition was not correct (bytes swaped). mohor 8167d 07h /ethmac/tags/rel_17
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8167d 09h /ethmac/tags/rel_17
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8167d 09h /ethmac/tags/rel_17

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