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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7883d 09h /ethmac/tags/rel_17
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7885d 14h /ethmac/tags/rel_17
235 rev 4. mohor 7886d 05h /ethmac/tags/rel_17
234 Figure list assed to the revision 3. mohor 7886d 13h /ethmac/tags/rel_17
233 Revision 0.3 released. Some figures added. mohor 7886d 13h /ethmac/tags/rel_17
232 fpga define added. mohor 7891d 08h /ethmac/tags/rel_17
231 Description of Core Modules added (figure). mohor 7893d 10h /ethmac/tags/rel_17
229 case changed to casex. mohor 7897d 06h /ethmac/tags/rel_17
227 Changed BIST scan signals. tadejm 7897d 10h /ethmac/tags/rel_17
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7897d 11h /ethmac/tags/rel_17
225 Some minor changes. tadejm 7897d 12h /ethmac/tags/rel_17
224 Signals for a wave window in Modelsim. tadejm 7897d 13h /ethmac/tags/rel_17
223 Some code changed due to bug fixes. tadejm 7897d 13h /ethmac/tags/rel_17
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7901d 11h /ethmac/tags/rel_17
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7904d 11h /ethmac/tags/rel_17
218 Typo error fixed. (When using Bist) mohor 7904d 13h /ethmac/tags/rel_17
217 Bist supported. mohor 7904d 14h /ethmac/tags/rel_17
216 Bist signals added. mohor 7904d 14h /ethmac/tags/rel_17
215 Bist supported. mohor 7904d 14h /ethmac/tags/rel_17
214 Signals for WISHBONE B3 compliant interface added. mohor 7905d 10h /ethmac/tags/rel_17
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7905d 10h /ethmac/tags/rel_17
212 Minor $display change. mohor 7905d 10h /ethmac/tags/rel_17
211 Bist added. mohor 7905d 11h /ethmac/tags/rel_17
210 BIST added. mohor 7905d 11h /ethmac/tags/rel_17
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7906d 14h /ethmac/tags/rel_17
208 Virtual Silicon RAMs moved to lib directory tadej 7922d 08h /ethmac/tags/rel_17
207 Virtual Silicon RAM support fixed tadej 7922d 08h /ethmac/tags/rel_17
206 Virtual Silicon RAM added to the simulation. mohor 7922d 08h /ethmac/tags/rel_17
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7922d 09h /ethmac/tags/rel_17
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7922d 09h /ethmac/tags/rel_17

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