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[/] [ethmac/] [tags/] [rel_17] - Rev 251

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251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7870d 22h /ethmac/tags/rel_17
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7870d 22h /ethmac/tags/rel_17
248 wb_rst_i is used for MIIM reset. mohor 7871d 22h /ethmac/tags/rel_17
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7875d 01h /ethmac/tags/rel_17
245 Rev 1.7. mohor 7875d 19h /ethmac/tags/rel_17
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7875d 21h /ethmac/tags/rel_17
243 Late collision is not reported any more. tadejm 7876d 02h /ethmac/tags/rel_17
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7876d 17h /ethmac/tags/rel_17
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7876d 17h /ethmac/tags/rel_17
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7876d 17h /ethmac/tags/rel_17
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7876d 17h /ethmac/tags/rel_17
238 Defines fixed to use generic RAM by default. mohor 7888d 21h /ethmac/tags/rel_17
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7891d 03h /ethmac/tags/rel_17
235 rev 4. mohor 7891d 17h /ethmac/tags/rel_17
234 Figure list assed to the revision 3. mohor 7892d 01h /ethmac/tags/rel_17
233 Revision 0.3 released. Some figures added. mohor 7892d 02h /ethmac/tags/rel_17
232 fpga define added. mohor 7896d 21h /ethmac/tags/rel_17
231 Description of Core Modules added (figure). mohor 7898d 22h /ethmac/tags/rel_17
229 case changed to casex. mohor 7902d 19h /ethmac/tags/rel_17
227 Changed BIST scan signals. tadejm 7902d 23h /ethmac/tags/rel_17
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7903d 00h /ethmac/tags/rel_17
225 Some minor changes. tadejm 7903d 00h /ethmac/tags/rel_17
224 Signals for a wave window in Modelsim. tadejm 7903d 01h /ethmac/tags/rel_17
223 Some code changed due to bug fixes. tadejm 7903d 02h /ethmac/tags/rel_17
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7906d 23h /ethmac/tags/rel_17
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7910d 00h /ethmac/tags/rel_17
218 Typo error fixed. (When using Bist) mohor 7910d 02h /ethmac/tags/rel_17
217 Bist supported. mohor 7910d 02h /ethmac/tags/rel_17
216 Bist signals added. mohor 7910d 02h /ethmac/tags/rel_17
215 Bist supported. mohor 7910d 03h /ethmac/tags/rel_17

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