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[/] [ethmac/] [tags/] [rel_17] - Rev 259

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259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7865d 11h /ethmac/tags/rel_17
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7865d 11h /ethmac/tags/rel_17
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7865d 11h /ethmac/tags/rel_17
255 TPauseRq synchronized to tx_clk. mohor 7865d 11h /ethmac/tags/rel_17
254 Temp version. mohor 7866d 15h /ethmac/tags/rel_17
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7866d 17h /ethmac/tags/rel_17
252 Just some updates. tadejm 7866d 18h /ethmac/tags/rel_17
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7866d 18h /ethmac/tags/rel_17
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7866d 18h /ethmac/tags/rel_17
248 wb_rst_i is used for MIIM reset. mohor 7867d 18h /ethmac/tags/rel_17
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7870d 21h /ethmac/tags/rel_17
245 Rev 1.7. mohor 7871d 15h /ethmac/tags/rel_17
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7871d 17h /ethmac/tags/rel_17
243 Late collision is not reported any more. tadejm 7871d 22h /ethmac/tags/rel_17
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7872d 13h /ethmac/tags/rel_17
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7872d 13h /ethmac/tags/rel_17
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7872d 13h /ethmac/tags/rel_17
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7872d 13h /ethmac/tags/rel_17
238 Defines fixed to use generic RAM by default. mohor 7884d 17h /ethmac/tags/rel_17
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7886d 22h /ethmac/tags/rel_17
235 rev 4. mohor 7887d 13h /ethmac/tags/rel_17
234 Figure list assed to the revision 3. mohor 7887d 21h /ethmac/tags/rel_17
233 Revision 0.3 released. Some figures added. mohor 7887d 21h /ethmac/tags/rel_17
232 fpga define added. mohor 7892d 16h /ethmac/tags/rel_17
231 Description of Core Modules added (figure). mohor 7894d 18h /ethmac/tags/rel_17
229 case changed to casex. mohor 7898d 14h /ethmac/tags/rel_17
227 Changed BIST scan signals. tadejm 7898d 18h /ethmac/tags/rel_17
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7898d 20h /ethmac/tags/rel_17
225 Some minor changes. tadejm 7898d 20h /ethmac/tags/rel_17
224 Signals for a wave window in Modelsim. tadejm 7898d 21h /ethmac/tags/rel_17

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