Rev |
Log message |
Author |
Age |
Path |
286 |
Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v. |
mohor |
7727d 05h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
253 |
r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
mohor |
7932d 23h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
246 |
Since r_Rst bit is not used any more, default value is changed to 0xa000. |
mohor |
7937d 03h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
238 |
Defines fixed to use generic RAM by default. |
mohor |
7950d 23h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
232 |
fpga define added. |
mohor |
7958d 22h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
213 |
Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added. |
mohor |
7973d 01h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
211 |
Bist added. |
mohor |
7973d 01h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
203 |
Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core. |
mohor |
7989d 23h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
145 |
Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). |
mohor |
8008d 23h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
137 |
Defines for register width added. mii_rst signal in MIIMODER register
changed. |
mohor |
8027d 19h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
134 |
Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more. |
mohor |
8029d 22h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
119 |
Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
mohor |
8052d 02h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
106 |
Outputs registered. Reset changed for eth_wishbone module. |
mohor |
8133d 07h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
105 |
Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed. |
mohor |
8142d 08h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
92 |
Some defines that are used in testbench only were moved to tb_eth_defines.v
file. |
mohor |
8178d 04h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
73 |
Number of interrupts changed |
mohor |
8199d 01h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
68 |
Registered trimmed. Unused registers removed. |
mohor |
8209d 03h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
67 |
EXTERNAL_DMA used instead of WISHBONE_DMA. |
mohor |
8209d 04h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
55 |
Changed that were lost with last update put back to the file. |
mohor |
8210d 06h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
52 |
Modified for Address Checking,
addition of eth_addrcheck.v |
billditt |
8210d 21h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
46 |
HASH0 and HASH1 registers added. |
mohor |
8213d 00h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
42 |
Rx status is written back to the BD. |
mohor |
8217d 01h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
40 |
Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed. |
mohor |
8220d 01h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
37 |
Link in the header changed. |
mohor |
8233d 07h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
34 |
RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors). |
mohor |
8282d 02h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
32 |
ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
mohor |
8282d 07h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
29 |
Generic memory model is used. Defines are changed for the same reason. |
mohor |
8304d 03h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
21 |
Status signals changed, Adress decoding changed, interrupt controller
added. |
mohor |
8330d 05h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
20 |
Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands). |
mohor |
8354d 02h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |
15 |
A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools. |
mohor |
8403d 03h |
/ethmac/tags/rel_18/rtl/verilog/eth_defines.v |