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[/] [ethmac/] [tags/] [rel_18/] [rtl/] [verilog/] [eth_top.v] - Rev 270

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Rev Log message Author Age Path
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7825d 13h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7885d 23h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 7887d 01h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7888d 07h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7888d 08h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 7889d 08h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7893d 07h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7894d 03h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7920d 08h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7927d 12h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7928d 09h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
210 BIST added. mohor 7928d 09h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7948d 08h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7956d 11h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7958d 15h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7959d 12h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7964d 07h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 8005d 07h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8013d 07h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8088d 15h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8099d 11h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8127d 12h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8154d 08h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8154d 09h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
70 Small fixes. mohor 8162d 15h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8164d 11h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8164d 12h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8164d 18h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8165d 12h /ethmac/tags/rel_18/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8165d 14h /ethmac/tags/rel_18/rtl/verilog/eth_top.v

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