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Rev Log message Author Age Path
235 rev 4. mohor 7901d 09h /ethmac/tags/rel_18
234 Figure list assed to the revision 3. mohor 7901d 17h /ethmac/tags/rel_18
233 Revision 0.3 released. Some figures added. mohor 7901d 18h /ethmac/tags/rel_18
232 fpga define added. mohor 7906d 13h /ethmac/tags/rel_18
231 Description of Core Modules added (figure). mohor 7908d 14h /ethmac/tags/rel_18
229 case changed to casex. mohor 7912d 11h /ethmac/tags/rel_18
227 Changed BIST scan signals. tadejm 7912d 15h /ethmac/tags/rel_18
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7912d 16h /ethmac/tags/rel_18
225 Some minor changes. tadejm 7912d 16h /ethmac/tags/rel_18
224 Signals for a wave window in Modelsim. tadejm 7912d 17h /ethmac/tags/rel_18
223 Some code changed due to bug fixes. tadejm 7912d 18h /ethmac/tags/rel_18
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7916d 16h /ethmac/tags/rel_18
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7919d 16h /ethmac/tags/rel_18
218 Typo error fixed. (When using Bist) mohor 7919d 18h /ethmac/tags/rel_18
217 Bist supported. mohor 7919d 18h /ethmac/tags/rel_18
216 Bist signals added. mohor 7919d 18h /ethmac/tags/rel_18
215 Bist supported. mohor 7919d 19h /ethmac/tags/rel_18
214 Signals for WISHBONE B3 compliant interface added. mohor 7920d 15h /ethmac/tags/rel_18
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7920d 15h /ethmac/tags/rel_18
212 Minor $display change. mohor 7920d 15h /ethmac/tags/rel_18
211 Bist added. mohor 7920d 15h /ethmac/tags/rel_18
210 BIST added. mohor 7920d 15h /ethmac/tags/rel_18
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7921d 18h /ethmac/tags/rel_18
208 Virtual Silicon RAMs moved to lib directory tadej 7937d 12h /ethmac/tags/rel_18
207 Virtual Silicon RAM support fixed tadej 7937d 12h /ethmac/tags/rel_18
206 Virtual Silicon RAM added to the simulation. mohor 7937d 13h /ethmac/tags/rel_18
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7937d 13h /ethmac/tags/rel_18
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7937d 13h /ethmac/tags/rel_18
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7937d 13h /ethmac/tags/rel_18
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7940d 14h /ethmac/tags/rel_18

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