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[/] [ethmac/] [tags/] [rel_18] - Rev 241

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241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7880d 08h /ethmac/tags/rel_18
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7880d 08h /ethmac/tags/rel_18
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7880d 08h /ethmac/tags/rel_18
238 Defines fixed to use generic RAM by default. mohor 7892d 12h /ethmac/tags/rel_18
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7894d 18h /ethmac/tags/rel_18
235 rev 4. mohor 7895d 08h /ethmac/tags/rel_18
234 Figure list assed to the revision 3. mohor 7895d 17h /ethmac/tags/rel_18
233 Revision 0.3 released. Some figures added. mohor 7895d 17h /ethmac/tags/rel_18
232 fpga define added. mohor 7900d 12h /ethmac/tags/rel_18
231 Description of Core Modules added (figure). mohor 7902d 13h /ethmac/tags/rel_18
229 case changed to casex. mohor 7906d 10h /ethmac/tags/rel_18
227 Changed BIST scan signals. tadejm 7906d 14h /ethmac/tags/rel_18
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7906d 15h /ethmac/tags/rel_18
225 Some minor changes. tadejm 7906d 15h /ethmac/tags/rel_18
224 Signals for a wave window in Modelsim. tadejm 7906d 16h /ethmac/tags/rel_18
223 Some code changed due to bug fixes. tadejm 7906d 17h /ethmac/tags/rel_18
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7910d 15h /ethmac/tags/rel_18
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7913d 15h /ethmac/tags/rel_18
218 Typo error fixed. (When using Bist) mohor 7913d 17h /ethmac/tags/rel_18
217 Bist supported. mohor 7913d 17h /ethmac/tags/rel_18
216 Bist signals added. mohor 7913d 17h /ethmac/tags/rel_18
215 Bist supported. mohor 7913d 18h /ethmac/tags/rel_18
214 Signals for WISHBONE B3 compliant interface added. mohor 7914d 14h /ethmac/tags/rel_18
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7914d 14h /ethmac/tags/rel_18
212 Minor $display change. mohor 7914d 14h /ethmac/tags/rel_18
211 Bist added. mohor 7914d 14h /ethmac/tags/rel_18
210 BIST added. mohor 7914d 14h /ethmac/tags/rel_18
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7915d 17h /ethmac/tags/rel_18
208 Virtual Silicon RAMs moved to lib directory tadej 7931d 11h /ethmac/tags/rel_18
207 Virtual Silicon RAM support fixed tadej 7931d 11h /ethmac/tags/rel_18

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