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[/] [ethmac/] [tags/] [rel_19/] [bench/] [verilog/] [tb_ethernet.v] - Rev 266

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266 Flow control test almost finished. mohor 7877d 23h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7878d 14h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7879d 02h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7880d 20h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7880d 23h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7886d 03h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 7912d 23h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 7913d 02h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7922d 03h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 7941d 02h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 7942d 22h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 7944d 22h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 7945d 01h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 7947d 21h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 7947d 22h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 7947d 22h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 7948d 01h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 7948d 04h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7948d 04h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 7953d 00h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 7955d 05h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8000d 00h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
117 Clock mrx_clk set to 2.5 MHz. mohor 8004d 02h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8004d 02h /ethmac/tags/rel_19/bench/verilog/tb_ethernet.v

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