OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [bench/] [verilog] - Rev 216

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
216 Bist signals added. mohor 7944d 16h /ethmac/tags/rel_19/bench/verilog
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7946d 16h /ethmac/tags/rel_19/bench/verilog
194 Full duplex tests modified and testbench bug repaired. tadej 7965d 15h /ethmac/tags/rel_19/bench/verilog
192 Some additional reports added tadej 7967d 11h /ethmac/tags/rel_19/bench/verilog
191 Bug repaired in eth_phy device tadej 7967d 11h /ethmac/tags/rel_19/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7967d 13h /ethmac/tags/rel_19/bench/verilog
188 PHY changed. tadej 7968d 09h /ethmac/tags/rel_19/bench/verilog
182 Full duplex test improved. tadej 7969d 11h /ethmac/tags/rel_19/bench/verilog
181 MIIM test look better. mohor 7969d 14h /ethmac/tags/rel_19/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7972d 10h /ethmac/tags/rel_19/bench/verilog
179 Beautiful tests merget together mohor 7972d 11h /ethmac/tags/rel_19/bench/verilog
178 Rearanged testcases mohor 7972d 11h /ethmac/tags/rel_19/bench/verilog
177 Bug in MIIM fixed. mohor 7972d 15h /ethmac/tags/rel_19/bench/verilog
170 Headers changed. mohor 7972d 17h /ethmac/tags/rel_19/bench/verilog
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7972d 17h /ethmac/tags/rel_19/bench/verilog
158 Typo fixed. mohor 7977d 13h /ethmac/tags/rel_19/bench/verilog
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7979d 18h /ethmac/tags/rel_19/bench/verilog
156 Valid testbench. mohor 7979d 18h /ethmac/tags/rel_19/bench/verilog
155 Minor changes. mohor 7979d 18h /ethmac/tags/rel_19/bench/verilog
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8022d 12h /ethmac/tags/rel_19/bench/verilog
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8024d 13h /ethmac/tags/rel_19/bench/verilog
117 Clock mrx_clk set to 2.5 MHz. mohor 8028d 15h /ethmac/tags/rel_19/bench/verilog
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8028d 15h /ethmac/tags/rel_19/bench/verilog
108 Testbench supports unaligned accesses. mohor 8105d 19h /ethmac/tags/rel_19/bench/verilog
107 TX_BUF_BASE changed. mohor 8105d 19h /ethmac/tags/rel_19/bench/verilog
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8150d 16h /ethmac/tags/rel_19/bench/verilog
80 Small fixes for external/internal DMA missmatches. mohor 8171d 12h /ethmac/tags/rel_19/bench/verilog
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8181d 16h /ethmac/tags/rel_19/bench/verilog
66 Testbench fixed, code simplified, unused signals removed. mohor 8181d 22h /ethmac/tags/rel_19/bench/verilog
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8183d 09h /ethmac/tags/rel_19/bench/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.