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Rev Log message Author Age Path
254 Temp version. mohor 7891d 18h /ethmac/tags/rel_19
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7891d 20h /ethmac/tags/rel_19
252 Just some updates. tadejm 7891d 21h /ethmac/tags/rel_19
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7891d 21h /ethmac/tags/rel_19
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7891d 21h /ethmac/tags/rel_19
248 wb_rst_i is used for MIIM reset. mohor 7892d 21h /ethmac/tags/rel_19
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7896d 00h /ethmac/tags/rel_19
245 Rev 1.7. mohor 7896d 18h /ethmac/tags/rel_19
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7896d 20h /ethmac/tags/rel_19
243 Late collision is not reported any more. tadejm 7897d 01h /ethmac/tags/rel_19
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7897d 16h /ethmac/tags/rel_19
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7897d 16h /ethmac/tags/rel_19
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7897d 16h /ethmac/tags/rel_19
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7897d 16h /ethmac/tags/rel_19
238 Defines fixed to use generic RAM by default. mohor 7909d 20h /ethmac/tags/rel_19
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7912d 01h /ethmac/tags/rel_19
235 rev 4. mohor 7912d 16h /ethmac/tags/rel_19
234 Figure list assed to the revision 3. mohor 7913d 00h /ethmac/tags/rel_19
233 Revision 0.3 released. Some figures added. mohor 7913d 01h /ethmac/tags/rel_19
232 fpga define added. mohor 7917d 19h /ethmac/tags/rel_19
231 Description of Core Modules added (figure). mohor 7919d 21h /ethmac/tags/rel_19
229 case changed to casex. mohor 7923d 17h /ethmac/tags/rel_19
227 Changed BIST scan signals. tadejm 7923d 21h /ethmac/tags/rel_19
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7923d 23h /ethmac/tags/rel_19
225 Some minor changes. tadejm 7923d 23h /ethmac/tags/rel_19
224 Signals for a wave window in Modelsim. tadejm 7924d 00h /ethmac/tags/rel_19
223 Some code changed due to bug fixes. tadejm 7924d 00h /ethmac/tags/rel_19
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7927d 22h /ethmac/tags/rel_19
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7930d 23h /ethmac/tags/rel_19
218 Typo error fixed. (When using Bist) mohor 7931d 01h /ethmac/tags/rel_19

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