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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7883d 01h /ethmac/tags/rel_20
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7885d 06h /ethmac/tags/rel_20
235 rev 4. mohor 7885d 21h /ethmac/tags/rel_20
234 Figure list assed to the revision 3. mohor 7886d 05h /ethmac/tags/rel_20
233 Revision 0.3 released. Some figures added. mohor 7886d 05h /ethmac/tags/rel_20
232 fpga define added. mohor 7891d 00h /ethmac/tags/rel_20
231 Description of Core Modules added (figure). mohor 7893d 02h /ethmac/tags/rel_20
229 case changed to casex. mohor 7896d 22h /ethmac/tags/rel_20
227 Changed BIST scan signals. tadejm 7897d 02h /ethmac/tags/rel_20
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7897d 04h /ethmac/tags/rel_20
225 Some minor changes. tadejm 7897d 04h /ethmac/tags/rel_20
224 Signals for a wave window in Modelsim. tadejm 7897d 05h /ethmac/tags/rel_20
223 Some code changed due to bug fixes. tadejm 7897d 05h /ethmac/tags/rel_20
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7901d 03h /ethmac/tags/rel_20
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7904d 04h /ethmac/tags/rel_20
218 Typo error fixed. (When using Bist) mohor 7904d 06h /ethmac/tags/rel_20
217 Bist supported. mohor 7904d 06h /ethmac/tags/rel_20
216 Bist signals added. mohor 7904d 06h /ethmac/tags/rel_20
215 Bist supported. mohor 7904d 07h /ethmac/tags/rel_20
214 Signals for WISHBONE B3 compliant interface added. mohor 7905d 02h /ethmac/tags/rel_20
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7905d 03h /ethmac/tags/rel_20
212 Minor $display change. mohor 7905d 03h /ethmac/tags/rel_20
211 Bist added. mohor 7905d 03h /ethmac/tags/rel_20
210 BIST added. mohor 7905d 03h /ethmac/tags/rel_20
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7906d 06h /ethmac/tags/rel_20
208 Virtual Silicon RAMs moved to lib directory tadej 7922d 00h /ethmac/tags/rel_20
207 Virtual Silicon RAM support fixed tadej 7922d 00h /ethmac/tags/rel_20
206 Virtual Silicon RAM added to the simulation. mohor 7922d 00h /ethmac/tags/rel_20
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7922d 01h /ethmac/tags/rel_20
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7922d 01h /ethmac/tags/rel_20

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