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[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog] - Rev 244

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Rev	Log message	Author	Age	Path
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7880d 05h	/ethmac/tags/rel_20/rtl/verilog
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7881d 01h	/ethmac/tags/rel_20/rtl/verilog
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7881d 01h	/ethmac/tags/rel_20/rtl/verilog
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7881d 02h	/ethmac/tags/rel_20/rtl/verilog
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7881d 02h	/ethmac/tags/rel_20/rtl/verilog
238	Defines fixed to use generic RAM by default.	mohor	7893d 06h	/ethmac/tags/rel_20/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7895d 11h	/ethmac/tags/rel_20/rtl/verilog
232	fpga define added.	mohor	7901d 05h	/ethmac/tags/rel_20/rtl/verilog
229	case changed to casex.	mohor	7907d 03h	/ethmac/tags/rel_20/rtl/verilog
227	Changed BIST scan signals.	tadejm	7907d 07h	/ethmac/tags/rel_20/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7907d 08h	/ethmac/tags/rel_20/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7911d 08h	/ethmac/tags/rel_20/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7914d 08h	/ethmac/tags/rel_20/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7914d 10h	/ethmac/tags/rel_20/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7915d 07h	/ethmac/tags/rel_20/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7915d 07h	/ethmac/tags/rel_20/rtl/verilog
212	Minor $display change.	mohor	7915d 07h	/ethmac/tags/rel_20/rtl/verilog
211	Bist added.	mohor	7915d 07h	/ethmac/tags/rel_20/rtl/verilog
210	BIST added.	mohor	7915d 07h	/ethmac/tags/rel_20/rtl/verilog
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7932d 06h	/ethmac/tags/rel_20/rtl/verilog
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7932d 06h	/ethmac/tags/rel_20/rtl/verilog
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7935d 07h	/ethmac/tags/rel_20/rtl/verilog
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7943d 09h	/ethmac/tags/rel_20/rtl/verilog
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7944d 10h	/ethmac/tags/rel_20/rtl/verilog
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7945d 10h	/ethmac/tags/rel_20/rtl/verilog
165	HASH improvement needed.	mohor	7945d 13h	/ethmac/tags/rel_20/rtl/verilog
164	Ethernet debug registers removed.	mohor	7945d 13h	/ethmac/tags/rel_20/rtl/verilog
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7946d 11h	/ethmac/tags/rel_20/rtl/verilog
160	error acknowledge cycle termination added to display.	mohor	7946d 11h	/ethmac/tags/rel_20/rtl/verilog
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7947d 07h	/ethmac/tags/rel_20/rtl/verilog

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[/] [ethmac/] [tags/] [rel_20/] [rtl/] [verilog] - Rev 244

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