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[/] [ethmac/] [tags/] [rel_21/] - Rev 269

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269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7818d 21h /ethmac/tags/rel_21
268 Release 1.19. Control frame description changed. mohor 7872d 14h /ethmac/tags/rel_21
267 Full duplex control frames tested. mohor 7872d 17h /ethmac/tags/rel_21
266 Flow control test almost finished. mohor 7877d 16h /ethmac/tags/rel_21
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7877d 20h /ethmac/tags/rel_21
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7878d 07h /ethmac/tags/rel_21
262 Version 1.18 released.
MIIMRST (Reset of the MIIM module) not used any more in the MIIMODER
register. Control Frame bit (CF) added to the RX buffer descriptor. Control
frame detection section updated.		 mohor 7878d 07h /ethmac/tags/rel_21
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7878d 07h /ethmac/tags/rel_21
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7878d 19h /ethmac/tags/rel_21
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7879d 09h /ethmac/tags/rel_21
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7879d 09h /ethmac/tags/rel_21
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7879d 09h /ethmac/tags/rel_21
255 TPauseRq synchronized to tx_clk. mohor 7879d 09h /ethmac/tags/rel_21
254 Temp version. mohor 7880d 13h /ethmac/tags/rel_21
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7880d 15h /ethmac/tags/rel_21
252 Just some updates. tadejm 7880d 15h /ethmac/tags/rel_21
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7880d 16h /ethmac/tags/rel_21
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7880d 16h /ethmac/tags/rel_21
248 wb_rst_i is used for MIIM reset. mohor 7881d 16h /ethmac/tags/rel_21
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7884d 19h /ethmac/tags/rel_21
245 Rev 1.7. mohor 7885d 12h /ethmac/tags/rel_21
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7885d 15h /ethmac/tags/rel_21
243 Late collision is not reported any more. tadejm 7885d 20h /ethmac/tags/rel_21
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7886d 11h /ethmac/tags/rel_21
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7886d 11h /ethmac/tags/rel_21
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7886d 11h /ethmac/tags/rel_21
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7886d 11h /ethmac/tags/rel_21
238 Defines fixed to use generic RAM by default. mohor 7898d 15h /ethmac/tags/rel_21
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7900d 20h /ethmac/tags/rel_21
235 rev 4. mohor 7901d 11h /ethmac/tags/rel_21

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