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[/] [ethmac/] [tags/] [rel_22/] - Rev 261

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Rev Log message Author Age Path
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7888d 03h /ethmac/tags/rel_22
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7888d 15h /ethmac/tags/rel_22
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7889d 04h /ethmac/tags/rel_22
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7889d 05h /ethmac/tags/rel_22
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7889d 05h /ethmac/tags/rel_22
255 TPauseRq synchronized to tx_clk. mohor 7889d 05h /ethmac/tags/rel_22
254 Temp version. mohor 7890d 09h /ethmac/tags/rel_22
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7890d 11h /ethmac/tags/rel_22
252 Just some updates. tadejm 7890d 11h /ethmac/tags/rel_22
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7890d 11h /ethmac/tags/rel_22
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7890d 11h /ethmac/tags/rel_22
248 wb_rst_i is used for MIIM reset. mohor 7891d 11h /ethmac/tags/rel_22
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7894d 15h /ethmac/tags/rel_22
245 Rev 1.7. mohor 7895d 08h /ethmac/tags/rel_22
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7895d 10h /ethmac/tags/rel_22
243 Late collision is not reported any more. tadejm 7895d 16h /ethmac/tags/rel_22
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7896d 06h /ethmac/tags/rel_22
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7896d 06h /ethmac/tags/rel_22
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7896d 07h /ethmac/tags/rel_22
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7896d 07h /ethmac/tags/rel_22
238 Defines fixed to use generic RAM by default. mohor 7908d 11h /ethmac/tags/rel_22
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7910d 16h /ethmac/tags/rel_22
235 rev 4. mohor 7911d 07h /ethmac/tags/rel_22
234 Figure list assed to the revision 3. mohor 7911d 15h /ethmac/tags/rel_22
233 Revision 0.3 released. Some figures added. mohor 7911d 15h /ethmac/tags/rel_22
232 fpga define added. mohor 7916d 10h /ethmac/tags/rel_22
231 Description of Core Modules added (figure). mohor 7918d 11h /ethmac/tags/rel_22
229 case changed to casex. mohor 7922d 08h /ethmac/tags/rel_22
227 Changed BIST scan signals. tadejm 7922d 12h /ethmac/tags/rel_22
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7922d 13h /ethmac/tags/rel_22

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