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[/] [ethmac/] [tags/] [rel_22] - Rev 248

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248 wb_rst_i is used for MIIM reset. mohor 7894d 14h /ethmac/tags/rel_22
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7897d 17h /ethmac/tags/rel_22
245 Rev 1.7. mohor 7898d 10h /ethmac/tags/rel_22
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7898d 13h /ethmac/tags/rel_22
243 Late collision is not reported any more. tadejm 7898d 18h /ethmac/tags/rel_22
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7899d 09h /ethmac/tags/rel_22
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7899d 09h /ethmac/tags/rel_22
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7899d 09h /ethmac/tags/rel_22
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7899d 09h /ethmac/tags/rel_22
238 Defines fixed to use generic RAM by default. mohor 7911d 13h /ethmac/tags/rel_22
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7913d 18h /ethmac/tags/rel_22
235 rev 4. mohor 7914d 09h /ethmac/tags/rel_22
234 Figure list assed to the revision 3. mohor 7914d 17h /ethmac/tags/rel_22
233 Revision 0.3 released. Some figures added. mohor 7914d 17h /ethmac/tags/rel_22
232 fpga define added. mohor 7919d 12h /ethmac/tags/rel_22
231 Description of Core Modules added (figure). mohor 7921d 14h /ethmac/tags/rel_22
229 case changed to casex. mohor 7925d 10h /ethmac/tags/rel_22
227 Changed BIST scan signals. tadejm 7925d 14h /ethmac/tags/rel_22
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7925d 16h /ethmac/tags/rel_22
225 Some minor changes. tadejm 7925d 16h /ethmac/tags/rel_22
224 Signals for a wave window in Modelsim. tadejm 7925d 17h /ethmac/tags/rel_22
223 Some code changed due to bug fixes. tadejm 7925d 17h /ethmac/tags/rel_22
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7929d 15h /ethmac/tags/rel_22
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7932d 16h /ethmac/tags/rel_22
218 Typo error fixed. (When using Bist) mohor 7932d 18h /ethmac/tags/rel_22
217 Bist supported. mohor 7932d 18h /ethmac/tags/rel_22
216 Bist signals added. mohor 7932d 18h /ethmac/tags/rel_22
215 Bist supported. mohor 7932d 19h /ethmac/tags/rel_22
214 Signals for WISHBONE B3 compliant interface added. mohor 7933d 14h /ethmac/tags/rel_22
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7933d 14h /ethmac/tags/rel_22

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