OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_23/] - Rev 254

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
254 Temp version. mohor 7866d 19h /ethmac/tags/rel_23
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7866d 21h /ethmac/tags/rel_23
252 Just some updates. tadejm 7866d 22h /ethmac/tags/rel_23
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7866d 22h /ethmac/tags/rel_23
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7866d 22h /ethmac/tags/rel_23
248 wb_rst_i is used for MIIM reset. mohor 7867d 22h /ethmac/tags/rel_23
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7871d 01h /ethmac/tags/rel_23
245 Rev 1.7. mohor 7871d 19h /ethmac/tags/rel_23
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7871d 21h /ethmac/tags/rel_23
243 Late collision is not reported any more. tadejm 7872d 02h /ethmac/tags/rel_23
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7872d 17h /ethmac/tags/rel_23
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7872d 17h /ethmac/tags/rel_23
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7872d 17h /ethmac/tags/rel_23
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7872d 17h /ethmac/tags/rel_23
238 Defines fixed to use generic RAM by default. mohor 7884d 21h /ethmac/tags/rel_23
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7887d 03h /ethmac/tags/rel_23
235 rev 4. mohor 7887d 17h /ethmac/tags/rel_23
234 Figure list assed to the revision 3. mohor 7888d 01h /ethmac/tags/rel_23
233 Revision 0.3 released. Some figures added. mohor 7888d 02h /ethmac/tags/rel_23
232 fpga define added. mohor 7892d 21h /ethmac/tags/rel_23
231 Description of Core Modules added (figure). mohor 7894d 22h /ethmac/tags/rel_23
229 case changed to casex. mohor 7898d 19h /ethmac/tags/rel_23
227 Changed BIST scan signals. tadejm 7898d 22h /ethmac/tags/rel_23
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7899d 00h /ethmac/tags/rel_23
225 Some minor changes. tadejm 7899d 00h /ethmac/tags/rel_23
224 Signals for a wave window in Modelsim. tadejm 7899d 01h /ethmac/tags/rel_23
223 Some code changed due to bug fixes. tadejm 7899d 01h /ethmac/tags/rel_23
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7902d 23h /ethmac/tags/rel_23
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7906d 00h /ethmac/tags/rel_23
218 Typo error fixed. (When using Bist) mohor 7906d 02h /ethmac/tags/rel_23

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.