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[/] [ethmac/] [tags/] [rel_23/] [bench/] [verilog/] - Rev 344

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Rev Log message Author Age Path
338 root 5609d 20h /ethmac/tags/rel_23/bench/verilog
335 New directory structure. root 5667d 01h /ethmac/tags/rel_23/bench/verilog
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7610d 17h /ethmac/tags/rel_23/bench/verilog
302 mbist signals updated according to newest convention markom 7637d 03h /ethmac/tags/rel_23/bench/verilog
299 Artisan RAMs added. mohor 7694d 23h /ethmac/tags/rel_23/bench/verilog
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7762d 23h /ethmac/tags/rel_23/bench/verilog
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7895d 19h /ethmac/tags/rel_23/bench/verilog
279 Underrun test fixed. Many other tests fixed. mohor 7896d 22h /ethmac/tags/rel_23/bench/verilog
274 Backup version. Not fully working. tadejm 7904d 16h /ethmac/tags/rel_23/bench/verilog
267 Full duplex control frames tested. mohor 7960d 19h /ethmac/tags/rel_23/bench/verilog
266 Flow control test almost finished. mohor 7965d 18h /ethmac/tags/rel_23/bench/verilog
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7966d 09h /ethmac/tags/rel_23/bench/verilog
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7966d 21h /ethmac/tags/rel_23/bench/verilog
254 Temp version. mohor 7968d 15h /ethmac/tags/rel_23/bench/verilog
252 Just some updates. tadejm 7968d 17h /ethmac/tags/rel_23/bench/verilog
243 Late collision is not reported any more. tadejm 7973d 22h /ethmac/tags/rel_23/bench/verilog
227 Changed BIST scan signals. tadejm 8000d 18h /ethmac/tags/rel_23/bench/verilog
223 Some code changed due to bug fixes. tadejm 8000d 21h /ethmac/tags/rel_23/bench/verilog
216 Bist signals added. mohor 8007d 22h /ethmac/tags/rel_23/bench/verilog
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8009d 22h /ethmac/tags/rel_23/bench/verilog
194 Full duplex tests modified and testbench bug repaired. tadej 8028d 21h /ethmac/tags/rel_23/bench/verilog
192 Some additional reports added tadej 8030d 17h /ethmac/tags/rel_23/bench/verilog
191 Bug repaired in eth_phy device tadej 8030d 17h /ethmac/tags/rel_23/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 8030d 18h /ethmac/tags/rel_23/bench/verilog
188 PHY changed. tadej 8031d 15h /ethmac/tags/rel_23/bench/verilog
182 Full duplex test improved. tadej 8032d 17h /ethmac/tags/rel_23/bench/verilog
181 MIIM test look better. mohor 8032d 20h /ethmac/tags/rel_23/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 8035d 16h /ethmac/tags/rel_23/bench/verilog
179 Beautiful tests merget together mohor 8035d 16h /ethmac/tags/rel_23/bench/verilog
178 Rearanged testcases mohor 8035d 16h /ethmac/tags/rel_23/bench/verilog

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