OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_23/] [rtl/] [verilog/] [eth_top.v] - Rev 270

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7809d 07h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7869d 17h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 7870d 19h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7872d 01h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7872d 02h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 7873d 02h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7877d 01h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7877d 21h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7904d 02h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7911d 06h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7912d 02h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
210 BIST added. mohor 7912d 03h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7932d 02h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7940d 04h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
164 Ethernet debug registers removed. mohor 7942d 09h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7943d 06h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7948d 00h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7989d 01h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7997d 00h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8072d 09h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8083d 05h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8111d 06h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8138d 02h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8138d 03h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
70 Small fixes. mohor 8146d 08h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8148d 05h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8148d 06h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8148d 12h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8149d 05h /ethmac/tags/rel_23/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8149d 07h /ethmac/tags/rel_23/rtl/verilog/eth_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.