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Rev Log message Author Age Path
235 rev 4. mohor 7998d 05h /ethmac/tags/rel_23
234 Figure list assed to the revision 3. mohor 7998d 13h /ethmac/tags/rel_23
233 Revision 0.3 released. Some figures added. mohor 7998d 14h /ethmac/tags/rel_23
232 fpga define added. mohor 8003d 09h /ethmac/tags/rel_23
231 Description of Core Modules added (figure). mohor 8005d 10h /ethmac/tags/rel_23
229 case changed to casex. mohor 8009d 07h /ethmac/tags/rel_23
227 Changed BIST scan signals. tadejm 8009d 10h /ethmac/tags/rel_23
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 8009d 12h /ethmac/tags/rel_23
225 Some minor changes. tadejm 8009d 12h /ethmac/tags/rel_23
224 Signals for a wave window in Modelsim. tadejm 8009d 13h /ethmac/tags/rel_23
223 Some code changed due to bug fixes. tadejm 8009d 14h /ethmac/tags/rel_23
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 8013d 11h /ethmac/tags/rel_23
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 8016d 12h /ethmac/tags/rel_23
218 Typo error fixed. (When using Bist) mohor 8016d 14h /ethmac/tags/rel_23
217 Bist supported. mohor 8016d 14h /ethmac/tags/rel_23
216 Bist signals added. mohor 8016d 14h /ethmac/tags/rel_23
215 Bist supported. mohor 8016d 15h /ethmac/tags/rel_23
214 Signals for WISHBONE B3 compliant interface added. mohor 8017d 11h /ethmac/tags/rel_23
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 8017d 11h /ethmac/tags/rel_23
212 Minor $display change. mohor 8017d 11h /ethmac/tags/rel_23
211 Bist added. mohor 8017d 11h /ethmac/tags/rel_23
210 BIST added. mohor 8017d 11h /ethmac/tags/rel_23
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8018d 14h /ethmac/tags/rel_23
208 Virtual Silicon RAMs moved to lib directory tadej 8034d 08h /ethmac/tags/rel_23
207 Virtual Silicon RAM support fixed tadej 8034d 08h /ethmac/tags/rel_23
206 Virtual Silicon RAM added to the simulation. mohor 8034d 08h /ethmac/tags/rel_23
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 8034d 09h /ethmac/tags/rel_23
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8034d 09h /ethmac/tags/rel_23
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 8034d 09h /ethmac/tags/rel_23
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 8037d 10h /ethmac/tags/rel_23

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