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Rev Log message Author Age Path
245 Rev 1.7. mohor 7910d 08h /ethmac/tags/rel_23
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7910d 10h /ethmac/tags/rel_23
243 Late collision is not reported any more. tadejm 7910d 16h /ethmac/tags/rel_23
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7911d 06h /ethmac/tags/rel_23
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7911d 06h /ethmac/tags/rel_23
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7911d 06h /ethmac/tags/rel_23
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7911d 07h /ethmac/tags/rel_23
238 Defines fixed to use generic RAM by default. mohor 7923d 11h /ethmac/tags/rel_23
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7925d 16h /ethmac/tags/rel_23
235 rev 4. mohor 7926d 07h /ethmac/tags/rel_23
234 Figure list assed to the revision 3. mohor 7926d 15h /ethmac/tags/rel_23
233 Revision 0.3 released. Some figures added. mohor 7926d 15h /ethmac/tags/rel_23
232 fpga define added. mohor 7931d 10h /ethmac/tags/rel_23
231 Description of Core Modules added (figure). mohor 7933d 11h /ethmac/tags/rel_23
229 case changed to casex. mohor 7937d 08h /ethmac/tags/rel_23
227 Changed BIST scan signals. tadejm 7937d 12h /ethmac/tags/rel_23
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7937d 13h /ethmac/tags/rel_23
225 Some minor changes. tadejm 7937d 13h /ethmac/tags/rel_23
224 Signals for a wave window in Modelsim. tadejm 7937d 15h /ethmac/tags/rel_23
223 Some code changed due to bug fixes. tadejm 7937d 15h /ethmac/tags/rel_23
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7941d 13h /ethmac/tags/rel_23
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7944d 13h /ethmac/tags/rel_23
218 Typo error fixed. (When using Bist) mohor 7944d 15h /ethmac/tags/rel_23
217 Bist supported. mohor 7944d 15h /ethmac/tags/rel_23
216 Bist signals added. mohor 7944d 15h /ethmac/tags/rel_23
215 Bist supported. mohor 7944d 16h /ethmac/tags/rel_23
214 Signals for WISHBONE B3 compliant interface added. mohor 7945d 12h /ethmac/tags/rel_23
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7945d 12h /ethmac/tags/rel_23
212 Minor $display change. mohor 7945d 12h /ethmac/tags/rel_23
211 Bist added. mohor 7945d 12h /ethmac/tags/rel_23

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