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[/] [ethmac/] [tags/] [rel_23] - Rev 45

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45 Ethernet Datasheet added. mohor 8206d 20h /ethmac/tags/rel_23
44 Ethernet Datasheet added to cvs. mohor 8206d 20h /ethmac/tags/rel_23
43 Tx status is written back to the BD. mohor 8207d 21h /ethmac/tags/rel_23
42 Rx status is written back to the BD. mohor 8210d 14h /ethmac/tags/rel_23
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8212d 16h /ethmac/tags/rel_23
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8213d 14h /ethmac/tags/rel_23
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8217d 18h /ethmac/tags/rel_23
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8226d 20h /ethmac/tags/rel_23
37 Link in the header changed. mohor 8226d 20h /ethmac/tags/rel_23
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8272d 18h /ethmac/tags/rel_23
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8275d 15h /ethmac/tags/rel_23
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8275d 16h /ethmac/tags/rel_23
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8275d 20h /ethmac/tags/rel_23
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8275d 20h /ethmac/tags/rel_23
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8275d 21h /ethmac/tags/rel_23
30 BD section updated. mohor 8277d 17h /ethmac/tags/rel_23
29 Generic memory model is used. Defines are changed for the same reason. mohor 8297d 16h /ethmac/tags/rel_23
28 New release. Name changed to lower case. mohor 8300d 08h /ethmac/tags/rel_23
27 File names changed to lower case. mohor 8300d 08h /ethmac/tags/rel_23
26 First release of product brief. mohor 8300d 08h /ethmac/tags/rel_23
25 First release of product brief. mohor 8300d 08h /ethmac/tags/rel_23
24 Log file added. mohor 8322d 19h /ethmac/tags/rel_23
23 Number of addresses (wb_adr_i) minimized. mohor 8322d 19h /ethmac/tags/rel_23
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8322d 22h /ethmac/tags/rel_23
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8323d 18h /ethmac/tags/rel_23
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8347d 15h /ethmac/tags/rel_23
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8347d 16h /ethmac/tags/rel_23
18 Few little NCSIM warnings fixed. mohor 8360d 16h /ethmac/tags/rel_23
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8387d 16h /ethmac/tags/rel_23
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8394d 22h /ethmac/tags/rel_23

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