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Rev Log message Author Age Path
233 Revision 0.3 released. Some figures added. mohor 7879d 16h /ethmac/tags/rel_24
232 fpga define added. mohor 7884d 11h /ethmac/tags/rel_24
231 Description of Core Modules added (figure). mohor 7886d 12h /ethmac/tags/rel_24
229 case changed to casex. mohor 7890d 09h /ethmac/tags/rel_24
227 Changed BIST scan signals. tadejm 7890d 13h /ethmac/tags/rel_24
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7890d 14h /ethmac/tags/rel_24
225 Some minor changes. tadejm 7890d 14h /ethmac/tags/rel_24
224 Signals for a wave window in Modelsim. tadejm 7890d 15h /ethmac/tags/rel_24
223 Some code changed due to bug fixes. tadejm 7890d 16h /ethmac/tags/rel_24
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7894d 14h /ethmac/tags/rel_24
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7897d 14h /ethmac/tags/rel_24
218 Typo error fixed. (When using Bist) mohor 7897d 16h /ethmac/tags/rel_24
217 Bist supported. mohor 7897d 16h /ethmac/tags/rel_24
216 Bist signals added. mohor 7897d 16h /ethmac/tags/rel_24
215 Bist supported. mohor 7897d 17h /ethmac/tags/rel_24
214 Signals for WISHBONE B3 compliant interface added. mohor 7898d 13h /ethmac/tags/rel_24
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7898d 13h /ethmac/tags/rel_24
212 Minor $display change. mohor 7898d 13h /ethmac/tags/rel_24
211 Bist added. mohor 7898d 13h /ethmac/tags/rel_24
210 BIST added. mohor 7898d 13h /ethmac/tags/rel_24
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7899d 16h /ethmac/tags/rel_24
208 Virtual Silicon RAMs moved to lib directory tadej 7915d 10h /ethmac/tags/rel_24
207 Virtual Silicon RAM support fixed tadej 7915d 10h /ethmac/tags/rel_24
206 Virtual Silicon RAM added to the simulation. mohor 7915d 11h /ethmac/tags/rel_24
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7915d 11h /ethmac/tags/rel_24
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7915d 11h /ethmac/tags/rel_24
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7915d 11h /ethmac/tags/rel_24
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7918d 12h /ethmac/tags/rel_24
201 Core size added to the document. mohor 7918d 13h /ethmac/tags/rel_24
200 File with lower case checked in instead. mohor 7918d 13h /ethmac/tags/rel_24

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