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Rev Log message Author Age Path
165 HASH improvement needed. mohor 7957d 07h /ethmac/tags/rel_26
164 Ethernet debug registers removed. mohor 7957d 07h /ethmac/tags/rel_26
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7957d 23h /ethmac/tags/rel_26
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7957d 23h /ethmac/tags/rel_26
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7958d 05h /ethmac/tags/rel_26
160 error acknowledge cycle termination added to display. mohor 7958d 05h /ethmac/tags/rel_26
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7959d 01h /ethmac/tags/rel_26
158 Typo fixed. mohor 7959d 02h /ethmac/tags/rel_26
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7961d 07h /ethmac/tags/rel_26
156 Valid testbench. mohor 7961d 07h /ethmac/tags/rel_26
155 Minor changes. mohor 7961d 07h /ethmac/tags/rel_26
154 Design document is still under construction. mohor 7962d 06h /ethmac/tags/rel_26
153 Temp version (backup). mohor 7962d 22h /ethmac/tags/rel_26
152 Version 1.16 created. See revision history in the document for details. mohor 7962d 22h /ethmac/tags/rel_26
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7962d 23h /ethmac/tags/rel_26
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7962d 23h /ethmac/tags/rel_26
148 Bug when last byte of destination address was not checked fixed. mohor 7962d 23h /ethmac/tags/rel_26
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7962d 23h /ethmac/tags/rel_26
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7962d 23h /ethmac/tags/rel_26
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7962d 23h /ethmac/tags/rel_26
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 7979d 02h /ethmac/tags/rel_26
141 Syntax error fixed. mohor 7981d 19h /ethmac/tags/rel_26
140 Syntax error fixed. mohor 7981d 20h /ethmac/tags/rel_26
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 7981d 20h /ethmac/tags/rel_26
138 Synchronous reset added. mohor 7981d 20h /ethmac/tags/rel_26
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7981d 20h /ethmac/tags/rel_26
136 Parameter ResetValue changed to capital letters. mohor 7982d 05h /ethmac/tags/rel_26
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 7983d 21h /ethmac/tags/rel_26
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7983d 22h /ethmac/tags/rel_26
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).		 mohor 7983d 23h /ethmac/tags/rel_26

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