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[/] [ethmac/] [tags/] [rel_26/] - Rev 244

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244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7875d 13h /ethmac/tags/rel_26
243 Late collision is not reported any more. tadejm 7875d 18h /ethmac/tags/rel_26
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7876d 09h /ethmac/tags/rel_26
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7876d 09h /ethmac/tags/rel_26
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7876d 09h /ethmac/tags/rel_26
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7876d 09h /ethmac/tags/rel_26
238 Defines fixed to use generic RAM by default. mohor 7888d 13h /ethmac/tags/rel_26
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7890d 19h /ethmac/tags/rel_26
235 rev 4. mohor 7891d 09h /ethmac/tags/rel_26
234 Figure list assed to the revision 3. mohor 7891d 17h /ethmac/tags/rel_26
233 Revision 0.3 released. Some figures added. mohor 7891d 18h /ethmac/tags/rel_26
232 fpga define added. mohor 7896d 13h /ethmac/tags/rel_26
231 Description of Core Modules added (figure). mohor 7898d 14h /ethmac/tags/rel_26
229 case changed to casex. mohor 7902d 11h /ethmac/tags/rel_26
227 Changed BIST scan signals. tadejm 7902d 15h /ethmac/tags/rel_26
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7902d 16h /ethmac/tags/rel_26
225 Some minor changes. tadejm 7902d 16h /ethmac/tags/rel_26
224 Signals for a wave window in Modelsim. tadejm 7902d 17h /ethmac/tags/rel_26
223 Some code changed due to bug fixes. tadejm 7902d 18h /ethmac/tags/rel_26
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7906d 15h /ethmac/tags/rel_26
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7909d 16h /ethmac/tags/rel_26
218 Typo error fixed. (When using Bist) mohor 7909d 18h /ethmac/tags/rel_26
217 Bist supported. mohor 7909d 18h /ethmac/tags/rel_26
216 Bist signals added. mohor 7909d 18h /ethmac/tags/rel_26
215 Bist supported. mohor 7909d 19h /ethmac/tags/rel_26
214 Signals for WISHBONE B3 compliant interface added. mohor 7910d 15h /ethmac/tags/rel_26
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7910d 15h /ethmac/tags/rel_26
212 Minor $display change. mohor 7910d 15h /ethmac/tags/rel_26
211 Bist added. mohor 7910d 15h /ethmac/tags/rel_26
210 BIST added. mohor 7910d 15h /ethmac/tags/rel_26

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