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[/] [ethmac/] [tags/] [rel_27/] [bench/] [verilog] - Rev 338

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338 root 5564d 03h /ethmac/tags/rel_27/bench/verilog
335 New directory structure. root 5621d 08h /ethmac/tags/rel_27/bench/verilog
324 This commit was manufactured by cvs2svn to create tag 'rel_27'. 7395d 08h /ethmac/tags/rel_27/bench/verilog
318 Latest Ethernet IP core testbench. tadejm 7430d 03h /ethmac/tags/rel_27/bench/verilog
315 Updated testbench. Some more testcases, some repaired. tadejm 7542d 06h /ethmac/tags/rel_27/bench/verilog
302 mbist signals updated according to newest convention markom 7591d 11h /ethmac/tags/rel_27/bench/verilog
299 Artisan RAMs added. mohor 7649d 06h /ethmac/tags/rel_27/bench/verilog
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7717d 07h /ethmac/tags/rel_27/bench/verilog
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7850d 03h /ethmac/tags/rel_27/bench/verilog
279 Underrun test fixed. Many other tests fixed. mohor 7851d 05h /ethmac/tags/rel_27/bench/verilog
274 Backup version. Not fully working. tadejm 7858d 23h /ethmac/tags/rel_27/bench/verilog
267 Full duplex control frames tested. mohor 7915d 02h /ethmac/tags/rel_27/bench/verilog
266 Flow control test almost finished. mohor 7920d 01h /ethmac/tags/rel_27/bench/verilog
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7920d 16h /ethmac/tags/rel_27/bench/verilog
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7921d 05h /ethmac/tags/rel_27/bench/verilog
254 Temp version. mohor 7922d 22h /ethmac/tags/rel_27/bench/verilog
252 Just some updates. tadejm 7923d 01h /ethmac/tags/rel_27/bench/verilog
243 Late collision is not reported any more. tadejm 7928d 05h /ethmac/tags/rel_27/bench/verilog
227 Changed BIST scan signals. tadejm 7955d 01h /ethmac/tags/rel_27/bench/verilog
223 Some code changed due to bug fixes. tadejm 7955d 05h /ethmac/tags/rel_27/bench/verilog
216 Bist signals added. mohor 7962d 05h /ethmac/tags/rel_27/bench/verilog
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7964d 05h /ethmac/tags/rel_27/bench/verilog
194 Full duplex tests modified and testbench bug repaired. tadej 7983d 04h /ethmac/tags/rel_27/bench/verilog
192 Some additional reports added tadej 7985d 01h /ethmac/tags/rel_27/bench/verilog
191 Bug repaired in eth_phy device tadej 7985d 01h /ethmac/tags/rel_27/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7985d 02h /ethmac/tags/rel_27/bench/verilog
188 PHY changed. tadej 7985d 22h /ethmac/tags/rel_27/bench/verilog
182 Full duplex test improved. tadej 7987d 01h /ethmac/tags/rel_27/bench/verilog
181 MIIM test look better. mohor 7987d 03h /ethmac/tags/rel_27/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7989d 23h /ethmac/tags/rel_27/bench/verilog

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