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[/] [ethmac/] [tags/] [rel_5/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7993d 12h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7995d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7999d 06h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8000d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 8008d 04h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8008d 18h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 8009d 07h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 8009d 10h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8076d 21h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8085d 22h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8111d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8115d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8121d 18h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8121d 18h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8131d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8131d 17h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8133d 00h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8138d 12h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8142d 14h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8142d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8153d 14h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8153d 19h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8153d 19h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8154d 10h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8156d 14h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
43 Tx status is written back to the BD. mohor 8157d 22h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
42 Rx status is written back to the BD. mohor 8160d 15h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8162d 17h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8163d 14h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8167d 18h /ethmac/tags/rel_5/rtl/verilog/eth_wishbone.v

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