Rev |
Log message |
Author |
Age |
Path |
161 |
Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set. |
mohor |
7944d 21h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
149 |
Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected. |
mohor |
7949d 16h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
125 |
RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted. |
mohor |
7990d 16h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
114 |
EXTERNAL_DMA removed. External DMA not supported. |
mohor |
7998d 16h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
106 |
Outputs registered. Reset changed for eth_wishbone module. |
mohor |
8074d 00h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
103 |
Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v |
mohor |
8084d 20h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
95 |
md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect. |
mohor |
8112d 21h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
80 |
Small fixes for external/internal DMA missmatches. |
mohor |
8139d 18h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
76 |
Interrupts changed in the top file |
mohor |
8139d 18h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
70 |
Small fixes. |
mohor |
8148d 00h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
68 |
Registered trimmed. Unused registers removed. |
mohor |
8149d 20h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
67 |
EXTERNAL_DMA used instead of WISHBONE_DMA. |
mohor |
8149d 21h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
65 |
Testbench fixed, code simplified, unused signals removed. |
mohor |
8150d 03h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
63 |
RxAbort is connected differently. |
mohor |
8150d 21h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
59 |
Changes that were lost when updating from 1.11 to 1.14 fixed. |
mohor |
8150d 23h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
52 |
Modified for Address Checking,
addition of eth_addrcheck.v |
billditt |
8151d 14h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
47 |
HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits. |
mohor |
8153d 17h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
43 |
Tx status is written back to the BD. |
mohor |
8155d 01h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
42 |
Rx status is written back to the BD. |
mohor |
8157d 18h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
41 |
non-DMA host interface added. Select the right configutation in eth_defines. |
mohor |
8159d 20h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
37 |
Link in the header changed. |
mohor |
8174d 00h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
34 |
RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors). |
mohor |
8222d 20h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
33 |
ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
mohor |
8223d 00h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
23 |
Number of addresses (wb_adr_i) minimized. |
mohor |
8269d 23h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
22 |
eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project. |
mohor |
8270d 02h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
21 |
Status signals changed, Adress decoding changed, interrupt controller
added. |
mohor |
8270d 22h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
20 |
Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands). |
mohor |
8294d 19h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
17 |
Signal names changed on the top level for easier pad insertion (ASIC). |
mohor |
8334d 20h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |
15 |
A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools. |
mohor |
8343d 20h |
/ethmac/tags/rel_7/rtl/verilog/eth_top.v |